ADV7401 Register Configuration

Hello,

I am using ADV7401 for decoding CVBS Input. I am facing an issue with NTSC and PAL Video outputs from the Chip. I was able to measure the Number of Pixels and Number of Lines of output coming out of the ADV7401 Chip. 

In case of NTSC, I am getting 720 pixels and 253 lines instead of 240. The output is shifted downwards on the monitor.

In case of PAL , I am getting 720 pixels and 288 lines. Here the output is moving up and down slightly.

Here are the Register Configuration of ADV7401,

Slave Address, Reg Address, Data - This is the format used below

{ 0x42, 0x0F, 0x80 }, //soft reset

{ 0x42, 0x01, 0xC8 }, //Square Pixel is disabled
{ 0x42, 0x00, 0x0E },  // CVBS Ain10
{ 0x42, 0x03, 0x0C },  // 8 Bit Mode
{ 0x42, 0x17, 0x41 },  // select SH1
{ 0x42, 0x1D, 0x47 },  // Enable 28MHz Crystal
{ 0x42, 0x31, 0x02 },  // Clears NEWAV_MODE, SAV/EAV to suit ADV video encoders
{ 0x42, 0x3A, 0x10 },  // Set Latch Clock & Power UP ADC 1 & ADC2 & ADC3& ADC4
{ 0x42, 0x3B, 0x80 },  // Enable External Bias
{ 0x42, 0x3D, 0xA2 },  // MWE Enable Manual Window, Colour Kill Threshold to 2
{ 0x42, 0x3E, 0x6A },  // BLM optimisation
{ 0x42, 0x3F, 0xA0 }, // BGB
{ 0x42, 0x67, 0x01 },  // Format 422
{ 0x42, 0x73, 0xD0 }, // Manual Gain Channels A,B,C
{ 0x42, 0x74, 0x04 }, // Manual Gain Channels A,B,C
{ 0x42, 0x75, 0x01 }, // Manual Gain Channels A,B,C
{ 0x42, 0x76, 0x00 }, // Manual Gain Channels A,B,C
{ 0x42, 0x77, 0x04 }, // Manual Offsets A to 64d & B,C to 512
{ 0x42, 0x78, 0x08 }, // Manual Offsets A to 64d & B,C to 512
{ 0x42, 0x79, 0x02 }, // Manual Offsets A to 64d & B,C to 512
{ 0x42, 0x7A, 0x00 }, // Manual Offsets A to 64d & B,C to 512
{ 0x42, 0x86, 0x0B }, // Enable stdi_line_count_mode
{ 0x42, 0xC5, 0x00 }, // Clamp Mode 0 for FB hc based
{ 0x42, 0xED, 0x12 }, // FB_CAP_RES,Enable Dynamic Fast Blank Mode
{ 0x42, 0xF3, 0x0F }, // Enable Anti Alias Filter on all ADCs
{ 0x42, 0x0E, 0x80 }, // ADI Recommended Setting
{ 0x42, 0x49, 0x01 }, // ADI Recommended Setting
{ 0x42, 0x52, 0x46 }, // ADI Recommended Setting
{ 0x42, 0x54, 0x00 }, // ADI Recommended Setting
{ 0x42, 0x7F, 0xFF }, // ADI Recommended Setting
{ 0x42, 0x81, 0x30 }, // ADI Recommended Setting
{ 0x42, 0x90, 0xC9 }, // ADI Recommended Setting
{ 0x42, 0x91, 0x40 }, // ADI Recommended Setting
{ 0x42, 0x92, 0x3C }, // ADI Recommended Setting
{ 0x42, 0x93, 0xCA }, // ADI Recommended Setting
{ 0x42, 0x94, 0xD5 }, // ADI Recommended Setting
{ 0x42, 0xB6, 0x08 }, // ADI Recommended Setting
{ 0x42, 0xC0, 0x9A }, // ADI Recommended Setting
{ 0x42, 0xCF, 0x50 }, // ADI Recommended Setting
{ 0x42, 0xD0, 0x4E }, // ADI Recommended Setting
{ 0x42, 0xD1, 0xB9 }, // ADI Recommended Setting
{ 0x42, 0xD6, 0xDD }, // ADI Recommended Setting
{ 0x42, 0xD7, 0xE2 }, // ADI Recommended Setting
{ 0x42, 0xE5, 0x51 }, // ADI Recommended Setting
{ 0x42, 0x0E, 0x00 }, // ADI Recommended Setting
{ 0x42, 0x0C, 0xE2 }, // changing input color
{ 0x42, 0x0D, 0x88 } // changing input color

CVBS AIN-10 – NTSC/PAL 16-bit 422 Output

These values are written to the decoder using I2C.

I want to know whether the issue is caused by these register settings or we have any other register values to be set to solve this issue.

Parents
  • +1
    •  Analog Employees 
    on Jul 23, 2021 9:51 AM

    Hi,

     In NTSC mode, Could you please try toggling the BT656-4 bit in the User Map, register 0x04 bit [7] & this bit will allow the user to select an output mode that is compatible with ITUR BT656-3/4 standard.

     Please note depend upon the receiver system whether it is ITU-R BT.656-3 or ITU-R BT.656-4.

     If the receiver system is expecting an ITU-R BT.656-4 output from the ADV7401, then this can result in 10 extra lines being output at the top of the screen.

      This generally occurs with NTSC CVBS video inputs but not with PAL CVBS inputs. This is because of difference in the blanking timing between the ITU-R BT.656-3 and ITU-R BT.656-4 standards for digitized NTSC.

    Thanks,

    Poornima

  • Thank you for your response, this one worked, I could get the NTSC properly now.

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