[ADV7282A-M] Spike (glitch) from LP mode to HS mode on MIPI-CSI output

Hi,

I have some questions about spike (glitch) from LP mode to HS mode on MIPI CSI output of ADV7282A-M.
I summarized the questions to an attached file "ADV7282A_M_spike(glitch)_from_LP_to_HS_on_MIPI_output.xlsx".
Please refer it.

Thank you!
Best regards.
Tamu

XLSX

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  • 0
    •  Analog Employees 
    on Jul 16, 2021 7:21 AM

    Hi Tamu-San,

            Please refer below comments from the expert,

            In AN-1337, expert used the university of New Hampshire MIPI reference termination board to terminate the MIPI output from the ADV728x. This MIPI reference termination board has switches that change the termination in LP and HS modes. These switches cause voltage spikes which highlight in AN-1337.
           In a real system with a MIPI receiver expert would not expect such large voltage spikes as shown in AN-1337.

         As part of the MIPI specification, the MIPI receiver needs to terminate the signals correctly. The termination required changes depending on the MIPI mode (e.g. high speed, low power mode etc). The receiver needs to detect the mode of operation and dynamically set its termination accordingly.

        It means that you have a very good termination switch in your MIPI receiver and in this case customers do not see such spikes.

        Please note that the clock signals will only appear correctly when properly terminated. Until proper termination is achieved then you will not be able to decode video data from the MIPI CSI-2 signals output by the ADV7280-M.

    Thanks,

    Poornima

  • Hi, Poornima-san,

    Thank you for your reply !

    Actually, my customer uses ADV7282A-M and he can see a spike (glitch) on his board when the MIPI changes from LP to HS.
    So he wants to judge whether it's OK or no good.
    I think it's no problem as long as the spike (glitch) is less than VIL max (550 mV) on the "Table 22 LP Receiver DC specifications" in "mipi D-PHY specification" document.
    Is this right? Is there any other parameter or spec which we should take care?

    The customer can see the spike (glitch) less than about 250mV on his board.
    I think it's no problem because it is less than VIL max (550 mV) on the "Table 22 LP Receiver DC spacifications" in "mipi D-PHY specification" document.
    What do you think?

    Thank you!
    Best regards.
    Tamu

  • +1
    •  Analog Employees 
    on Jul 18, 2021 3:41 PM in reply to Tamu

    Hi Tamu-San,

           I believe Yes, As per figure 48 and Table 22 in MIPI D-PHY specification document, It doesn't cause any problem if it is less than the VIL max(550 mv).

           Also in Table 23 its like "LP receiver shall reject any input signal smaller than eSPIKE". 

           

    Thanks,

    Poornima

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