ADV7343 Progressive Mode settings

Hello,
I am working on ADV7343 encoder IC

Initially I configured the register set of ADV7343 IC for interlaced video for resolution 720*576 @25I
Pixel clock = 13.5MHz
CLKIN_A = 27MHz
The input to the encoder chipset is 16-bit YCrCb input in SD mode and output from the DAC is CVBS
The following main register of ADV7343 was configured to:-
0x88 = 0x08 //16-bit YCrCb input
0x02 = 0x60 //Sync output 
0x8A = 0x0C //timing mode

Hsync and VSync both are active low signal
The expected output was observed

Now If I need progressive video output from the encoder chip for resolution 720*576 @50P
Pixel clock = 27MHz
CLKIN_A = 27MHz
The input to the encoder chipset is 16-bit YCrCb input in SD mode and output from the DAC is CVBS, then with respect to above register set configuration the change will be only in the register set 0x88,bit 1 for the progressive mode.
0x88 = 0x0A
Hsync and VSync both are active low signal
The expected output is not observed, shift is observed at the output


Is there any other register set configuration to be done for progressive?

Thanks & Regards,
Arpitha

Parents
  • Hi,

      Please configure the 0x80 register for PAL because by default it will be in NTSC input. Refer below snap for your reference.

      

    Thanks,

    Poornima

  • Hello,

    The 0x80 register is configured to PAL with 0x11 value

    Can we get progressive video in SD mode?

    Like in SD mode we have only two synchronization signals Vsync and Hsync,

    For progressive we need Data valid signal, am I correct ?

    Thanks & Regards,

    Arpitha

  • Hi,

     Please note that, If any impedance mis-match could also cause an color issue, so expert suggested a simple tool here that can give you a first pass estimate of what the trace impedance is for various board stack ups and trace widths. Please crosscheck with your board with impedence calculator  PCB Trace Impedance Calculator - Documents - Video - EngineerZone

    Please try to configure SD chroma filter(0x80[7:5]) with different frequency and let us know whether you got any improvement.

    Also make sure the below DAC output registers are configured in right way.

    And ensure DAC outputs are operating in correct mode, Since DAC4 will operate only in low-drive mode.

     

    Note: FPGA clock outputs are not very stable or accurate.  This may cause color distortion and this is why you will see all our reference designs using crystals or oscillators for the 27MHz source. 

    Thanks,

    Poornima

  • Hello,

    I have enabled the internal test pattern of the encoder ADV7343 IC

    This are the following configurations done:-

    {0x56,0x17,0x02},
    {0x56,0x00,0xFC},
    {0x56,0x02,0x10},
    {0x56,0x82,0xC0},
    {0x56,0x84,0x40},
    {0x56,0x8C,0xCB},
    {0x56,0x8D,0x8A},
    {0x56,0x8E,0x09},
    {0x56,0x8F,0x2A},

    The color bar should be white, yellow, cyan, green, pink, red, blue, black

    But i am observing the following attached test patterns from DAC 4 (CVBS) and RGB from DAC 1,2,3

    because of the display size the white color is not seen, but in DAC 4 we are not able to get the expected

    color

    Thanks & Regards,

    Arpitha

      (1)From DAC4

    (2)From DAC 1,2 and 3

  • Hi,

      For internal test pattern generation, Some of the below register configuration seems indifferent.

      Kindly let us know, whether you have configured this for some specific purpose.

    PAL test pattern: Please make sure with below register settings,

         0x17  - 0x02

        0x00 - 0xFC

        0x82 - 0xC9

        0x84 - 0x40

        0x80 - 0x11

        0x8C - 0xCB

        0x8D - 0x8A

        0x8E - 0x09

        0x8F - 0x2A

    NTSC color test pattern: Please make sure with below register settings,

        0x17  - 0x02

        0x00 - 0xFC

        0x82 - 0xC9

    Thanks,

    Poornima

  • Hello

    Thank you for the response

    PAL test pattern: Please make sure with below register settings :-  I tested with this register settings mentioned here but the observation is same as before.

    Thanks & Regards,

    Arpitha

  • Hi,

      Please check with other ADV734x part , the test pattern should work if you follow the standard scripts and you sure that stable 27MHZ is applied to the CLKIN.

     Also make sure with FPGA whether the data stream from the FPGA is correct. 

    Thanks,

    Poornima

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