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ADV7343 Progressive Mode settings

Hello,
I am working on ADV7343 encoder IC

Initially I configured the register set of ADV7343 IC for interlaced video for resolution 720*576 @25I
Pixel clock = 13.5MHz
CLKIN_A = 27MHz
The input to the encoder chipset is 16-bit YCrCb input in SD mode and output from the DAC is CVBS
The following main register of ADV7343 was configured to:-
0x88 = 0x08 //16-bit YCrCb input
0x02 = 0x60 //Sync output 
0x8A = 0x0C //timing mode

Hsync and VSync both are active low signal
The expected output was observed

Now If I need progressive video output from the encoder chip for resolution 720*576 @50P
Pixel clock = 27MHz
CLKIN_A = 27MHz
The input to the encoder chipset is 16-bit YCrCb input in SD mode and output from the DAC is CVBS, then with respect to above register set configuration the change will be only in the register set 0x88,bit 1 for the progressive mode.
0x88 = 0x0A
Hsync and VSync both are active low signal
The expected output is not observed, shift is observed at the output


Is there any other register set configuration to be done for progressive?

Thanks & Regards,
Arpitha

Parents Reply
  • Hi,

      For internal test pattern generation, Some of the below register configuration seems indifferent.

      Kindly let us know, whether you have configured this for some specific purpose.

    PAL test pattern: Please make sure with below register settings,

         0x17  - 0x02

        0x00 - 0xFC

        0x82 - 0xC9

        0x84 - 0x40

        0x80 - 0x11

        0x8C - 0xCB

        0x8D - 0x8A

        0x8E - 0x09

        0x8F - 0x2A

    NTSC color test pattern: Please make sure with below register settings,

        0x17  - 0x02

        0x00 - 0xFC

        0x82 - 0xC9

    Thanks,

    Poornima

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