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ADV7343 Progressive Mode settings

Hello,
I am working on ADV7343 encoder IC

Initially I configured the register set of ADV7343 IC for interlaced video for resolution 720*576 @25I
Pixel clock = 13.5MHz
CLKIN_A = 27MHz
The input to the encoder chipset is 16-bit YCrCb input in SD mode and output from the DAC is CVBS
The following main register of ADV7343 was configured to:-
0x88 = 0x08 //16-bit YCrCb input
0x02 = 0x60 //Sync output 
0x8A = 0x0C //timing mode

Hsync and VSync both are active low signal
The expected output was observed

Now If I need progressive video output from the encoder chip for resolution 720*576 @50P
Pixel clock = 27MHz
CLKIN_A = 27MHz
The input to the encoder chipset is 16-bit YCrCb input in SD mode and output from the DAC is CVBS, then with respect to above register set configuration the change will be only in the register set 0x88,bit 1 for the progressive mode.
0x88 = 0x0A
Hsync and VSync both are active low signal
The expected output is not observed, shift is observed at the output


Is there any other register set configuration to be done for progressive?

Thanks & Regards,
Arpitha

Parents Reply
  • Hi,

     Please try to disable the PLL and check whether the noise disappears.

      If the the issue disappears with the PLL disabled is a good indicator that the problem lies in the external loop filter circuitry. The external loop filter circuit is extremely sensitive, and connecting it to an unfiltered supply will most likely in all cases lead to poor performance.

    Any noise on the external loop filter circuit supply can cause an poor performance.

    Please ensure with reference schematic and Is the external loop filter circuit connected directly to the PVDD supply without supply filtered (i.e EXT_LF filter parts directly to 1.8V without filter caps)

    Thanks,

    Poornima

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