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ADV7343 Progressive Mode settings

Hello,
I am working on ADV7343 encoder IC

Initially I configured the register set of ADV7343 IC for interlaced video for resolution 720*576 @25I
Pixel clock = 13.5MHz
CLKIN_A = 27MHz
The input to the encoder chipset is 16-bit YCrCb input in SD mode and output from the DAC is CVBS
The following main register of ADV7343 was configured to:-
0x88 = 0x08 //16-bit YCrCb input
0x02 = 0x60 //Sync output 
0x8A = 0x0C //timing mode

Hsync and VSync both are active low signal
The expected output was observed

Now If I need progressive video output from the encoder chip for resolution 720*576 @50P
Pixel clock = 27MHz
CLKIN_A = 27MHz
The input to the encoder chipset is 16-bit YCrCb input in SD mode and output from the DAC is CVBS, then with respect to above register set configuration the change will be only in the register set 0x88,bit 1 for the progressive mode.
0x88 = 0x0A
Hsync and VSync both are active low signal
The expected output is not observed, shift is observed at the output


Is there any other register set configuration to be done for progressive?

Thanks & Regards,
Arpitha

Parents Reply
  • Hi,

       For ED mode with 576P , the encoder clock will be 27 MHZ , according to table 1 am i correct ?

         Yes.

      According to the ED output configuration, as mentioned in table 38, is it we can only use DAC 1,2 and 3 for ED and HD mode output ?

          Yes, you can use DAC1/DAC2/DAC3 for ED/HD output configuration.

    But in SD mode you can use upto six DACs.

    Thanks,

    Poornima

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