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ADV7343 Progressive Mode settings

Hello,
I am working on ADV7343 encoder IC

Initially I configured the register set of ADV7343 IC for interlaced video for resolution 720*576 @25I
Pixel clock = 13.5MHz
CLKIN_A = 27MHz
The input to the encoder chipset is 16-bit YCrCb input in SD mode and output from the DAC is CVBS
The following main register of ADV7343 was configured to:-
0x88 = 0x08 //16-bit YCrCb input
0x02 = 0x60 //Sync output 
0x8A = 0x0C //timing mode

Hsync and VSync both are active low signal
The expected output was observed

Now If I need progressive video output from the encoder chip for resolution 720*576 @50P
Pixel clock = 27MHz
CLKIN_A = 27MHz
The input to the encoder chipset is 16-bit YCrCb input in SD mode and output from the DAC is CVBS, then with respect to above register set configuration the change will be only in the register set 0x88,bit 1 for the progressive mode.
0x88 = 0x0A
Hsync and VSync both are active low signal
The expected output is not observed, shift is observed at the output


Is there any other register set configuration to be done for progressive?

Thanks & Regards,
Arpitha

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  • Hello,

    The 0x80 register is configured to PAL with 0x11 value

    Can we get progressive video in SD mode?

    Like in SD mode we have only two synchronization signals Vsync and Hsync,

    For progressive we need Data valid signal, am I correct ?

    Thanks & Regards,

    Arpitha

  • Hi,

     Can we get progressive video in SD mode?

       Yes you can, ADV734x can support an SD non-interlaced mode.

       Using this mode, progressive inputs at twice the frame rate of NTSC and PAL (240p/59.94 Hz and 288p/50 Hz, respectively) can be input into the ADV734x. Please refer Page54 in ADV734x datasheet.

    For progressive we need Data valid signal, am I correct ?

        No not required, When you look into the configuration for progressive input they have used only HSYNC/VSYNC synchronization format.

        Please note that when you want to measure at output side in that case normally interlaced formats use VS, HS and Field only.  DE doesn't make sense since the active video width is different depending on odd/even field. So only progressive formats can really use DE.
     

    Thanks,

    Poornima

  • Hello Poornima,

    Thank you for the response.

    In SD mode to get progressive output can the resolution be set to 576p?

    From the FPGA 16-bit data input, clock of 27MHz and Hsync (active low) and Vsync (active low) is given as an input to the encoder.

    Is there any timing setting to be done for the encoder register set configuration for progressive

    Thanks and Regards,

    Arpitha

  • Hi,

    Is there any timing setting to be done for the encoder register set configuration for progressive

      No not required, Your register configuration is enough by including the register setting 0x80 as 0x11 for the resolution 576p (PAL standard).

    Thanks,

    Poornima

  • Hi,

    I have included it.

    but still I am not getting the expected output.

    {0x56,0x80,0x11},
    {0x56,0x82,0x49},
    {0x56,0x83,0x04},
    {0x56,0x84,0x00},
    {0x56,0x86,0x02},
    {0x56,0x87,0x20},
    {0x56,0x88,0x0A},
    {0x56,0x89,0x00},
    {0x56,0x8A,0x0C},

    Thanks and Regards,

    Arpitha

  • Hi,

     If you are interleaving the Y with Cb/Cr with 16bit it would require the 54Mhz clock, So could you please try with ED/HD mode instead of SD mode and let us know the result.

    Thanks,

    Poornima

  • Hello,

    Thank you for the response

    I will check this and let you know.

    If in case instead of giving any NTSC or PAL input to the encoder, if a test pattern generator output is given than what should be the changes in the register value, can the 0x80 register be set to PAL or NTSC?

    Thanks,

    Arpitha

  • Hi,

    Can the 0x80 register be set to PAL or NTSC ?

       Yes, 0x80 register need to set accordingly for PAL and NTSC input for internal test pattern.

    Internal test pattern related configuration are detaily explained in Page82 of ADV734x datasheet.

    Note: SD Test Pattern- 27Mhz clock signal must be applied to the CLKIN pin.
               ED Test Pattern- 27Mhz clock signal must be applied to the CLKIN pin.
               HD Test Pattern- 74.25MHz clock signal must be applied to the CLKIN pin.
               For ED/HD internal test patterns Sub-address 0x31, Bit 2 = 1 should be enable. 

    Thanks,

    Poornima

  • Hello,

    Thanks for the info.

    Regarding the testing of progressive output from the encoder, in ED mode

    The resolution is set to 576p, the input clock to the encoder is 54Mhz,

    and the video data (16-bit YCrCb) , the active low signal hsync and vsync and the hblank from the FPGA is connected to the encoder P-HSYNC,P-VSYNC,P-Blank.

    The following register set are configured for ED mode,

    {0x56,0x00,0xFC},
    {0x56,0x01,0x70},
    {0x56,0x02,0xA0},
    {0x56,0x30,0x00},
    {0x56,0x31,0x01},
    {0x56,0x32,0x00},
    {0x56,0x33,0x68},
    {0x56,0x34,0x40},

    {0x56,0x80,0x11},
    {0x56,0x82,0x49},
    {0x56,0x83,0x04},
    {0x56,0x84,0x00},
    {0x56,0x86,0x02},
    {0x56,0x87,0x20},
    {0x56,0x88,0x0A},
    {0x56,0x89,0x00},
    {0x56,0x8A,0x0C},

    Can you please go through the register set configuration done by me, as there is no output seen in the display.

    Thanks,

    Arpitha

  • Hi,

       Most of your register configuration are different when we compare with table 103. Refer below snap to crosscheck your IN and OUT format.

     Please configure your registers as per table 103 and let us know the result.

    Thanks,

    Poornima