looking for 10 bit parallel video data to MIPI CSI 2 converting SerDes IC

Hi,

  ADV7480/ADV7481/ADV7482 are the chipsets that can convert 8-bit parallel video data input into MIPI CSI 2 output. Please refer below snap of ADV7482 for your reference.

Reference: Selection Table for MIPI Video Devices | Parametric Search | Analog Devices

Thanks,

Poornima

Hi Poornima,

Thanks for the response. 

I am not able to see the input pins of HS,VS,DE and PCLK. Then how can we connect this 8 bit parallel data with this component?

Regards,

Hi,

   Yes, you can give the 8 bit parallel video input using LLC / P0-P7 pins to ADV748x chipset.

    But for MIPI CSI 2 output i don't think we need HS,VS,DE input.

    Please note that, it should be required only when transmitting video data across the TMDS interface, then it is necessary to have an Hsync, Vsync, and Data Enable (DE) defined for the image

Thanks,

Poornima

Hi Poornima,

Is there any Eval kit available for ADV7482 for testing?

Regards,

Ameenu

Hi,

 Yes, Eval kit is available for ADV7482. Here you can get the more details about ADV7482 eval kit at    ADV748x_Evaluation_Board_Documents.zip

 Please refer here for getting the purchasing details about the ADV7482 Eval board at https://www.analog.com/en/products/adv7482.html#product-discussions

Thanks,

Poornima

Hi Poornima,

In Page no : 19 of ADV7482 datasheet, Following lines are mentioned.

"The following formats are supported both as input and output ports:

• 8-bit interleaved 4:2:2 SDR input/output with embedded timing codes

• 8-bit interleaved 4:2:2 DDR input/output with embedded timing codes"

But our input video is 8/10 bit RGB parallel video with Hsync, Vsync and Pixel clock(PCLK- 8MHz),

I am afraid of that whether it is compatible or not.

Regards,

Ameenu 

Hi Poornima,

In Page no : 19 of ADV7482 datasheet, Following lines are mentioned.

"The following formats are supported both as input and output ports:

• 8-bit interleaved 4:2:2 SDR input/output with embedded timing codes

• 8-bit interleaved 4:2:2 DDR input/output with embedded timing codes"

But our input video is 8/10 bit RGB parallel video with Hsync, Vsync and Pixel clock(PCLK- 8MHz),

I am afraid of that whether it is compatible or not.

Regards,

Ameenu 

Hi,

  Please note that in ADV748x the TTL/Digital input port (i.e Parallel input) which does not support any external sync signals.

  Since your requirement is for converting the parallel video data input to MIPI CSI-2, So don't use the sync pins and just connect the unused pins to ground.

Thanks,

Poornima

Hi Poornima,

Thanks for the response.

In Page No-9 of data sheet, Minimum Input LLC Clock frequency is 13.5MHz. But our PCLK is 8MHz only. Is it compatible to work properly?

Regards,

Ameenu

Hi,

   To avoid any glitches we should use as per datasheet specification of minimum and maximum requirement of LLC clock frequency.

   Please note that, If it is an different clock, the data would aligned to it but it obviously is not going to work with a different unaligned clock-- " it's probably not sampling the correct pixels ".

Thanks,

Poornima

Hi Poornima,

We can not configure the PCLK. Since it is 8Mhz, you are saying that, if we use this component (ADV7482),Glitches may happen. right?

Is there any other component available as per our requirement ?

Regards,

Ameenu

Hi,

  Yes, We will check any other component or part is available to meet your requirement.

Thanks,

Poornima

Hi,

I would like to remind you in case you missed to reply back

Regards

Ameenu

Hi,

  All our part requires minimum LLC clock frequency of 13.5Mhz, Since this is an nominal frequency.

Thanks,

Poornima