ADV7619:SDR 4:2:2 Output Modes 16Bit,can support resolution 4K@30Hz,another word,can clk up to 297MHz

ADV7619:SDR 4:2:2 Output Modes 16Bit,can support resolution 4K@30Hz,another word,can clk up to 297MHz

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  • 0
    •  Analog Employees 
    on Jun 9, 2021 8:45 AM

    Hi,

    ADV7619:SDR 4:2:2 Output Modes 16Bit,can support resolution 4K@30Hz,another word,can clk up to 297MHz

       Yes, its possible for 4k@30 in 16 bit SDR 4:2:2 mode.

       Please note that SDR is supported upto 170 MHz LLC frequency (UXGA, 1080p60 for any OP_FORMAT_SEL or up to 300 MHz HDMI signals output on two 24-bit parallel video sub buses OP_FORMAT_SEL = 0x94, 0x95, 0x96, or 0x54; refer to Table 12).

    Thanks,

    poornima.S

  • Thank you for you reply!

        our MCU only support 16Bit BT1120 or 8Bit BT656,both of them support SDR and DDR.
        SDR mode , clk up to 300MHz;
        DDR mode , clk up to 148.5MHz;
        so we only can use OP_FORMAT_SEL=0x80 or 0x20
       
        for the real world test,when OP_FORMAT_SEL=0x80,1080P@60 work perfect,but 4k@30Hz,the clock is unnormal,we can not catch stable 297MHz by oscilloscope.
        can you give some device  ?
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  • Thank you for you reply!

        our MCU only support 16Bit BT1120 or 8Bit BT656,both of them support SDR and DDR.
        SDR mode , clk up to 300MHz;
        DDR mode , clk up to 148.5MHz;
        so we only can use OP_FORMAT_SEL=0x80 or 0x20
       
        for the real world test,when OP_FORMAT_SEL=0x80,1080P@60 work perfect,but 4k@30Hz,the clock is unnormal,we can not catch stable 297MHz by oscilloscope.
        can you give some device  ?
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  • 0
    •  Analog Employees 
    on Jun 10, 2021 9:56 AM in reply to kim0716

    Hi,

        As mentioned earlier, for 4K30 please configure the OP_FORMAT_SEL register as  = 0x94, 0x95, 0x96, or 0x54; and let us know the result.

      Can you please crosscheck your configuration with reference script " ##03 HDMI Input to ADV7619, Input Pixel Frequency > 170MHz ## ".

     Please note that, For resolutions higher than 1080p, the video signals are routed directly to the pixel bus output as two 24-bit (4:4:4) buses running at up to 150 MHz. So you need to configure the OP_FORMAT_SEL  as "0x94/ 0x95/0x96/0x54".

      In this mode, the output data format is the same as the input format - i.e  for resolutions higher than 1080p, the video signal bypasses the CP block.

    Thanks,

    Poornima

  • Thank you for your reply!

    TXT is  ADV7619 register configurition,under that configuration,MCU can not get any data from the output

    The pdf is  ADV7619 hardware schematic diagram。

    Under these condition,can make 4k@30Hz work without change ADV7619 hardware schematic diagram?

    reg_config.txt
    {0x68,0xC0,0x03},// ADI Required Write
    {0x98,0x00,0x02},// Set VID_STD
    {0x98,0x01,0x06},// Prim_Mode =101b HDMI-Comp
    {0x98,0x02,0xF0},// Auto CSC, YCbCr out, Set op_656 bit
    {0x98,0x03,0x54},// 2x24 bit SDR 422 interleaved mode 0
    {0x98,0x05,0x28},// AV Codes Off
    {0x98,0x06,0xA0},// No inversion on VS,HS pins
    {0x98,0x0C,0x42},// Power up part
    {0x98,0x15,0x80},// Disable Tristate of Pins
    {0x98,0x19,0x83},// LLC DLL phase
    {0x98,0x33,0x40},// LLC DLL MUX enable
    {0x98,0xDD,0xa0},// ADI Required Write//gai----
    {0x98,0xE7,0x04},// ADI Required Write 
    {0x4C,0xB5,0x01},// Setting MCLK to 256Fs
    {0x4C,0xC3,0x80},// ADI Required Write
    {0x4C,0xCF,0x03},// ADI Required Write
    {0x4C,0xDB,0x80},// ADI Required Write
    {0x68,0xC0,0x03},// ADI Required write
    {0x68,0x00,0x08},// Set HDMI Input Port A (BG_MEAS_PORT_SEL = 001b)
    {0x68,0x02,0x03},// ALL BG Ports enabled
    {0x68,0x03,0x98},// ADI Required Write
    {0x68,0x10,0xA5},// ADI Required Write
    {0x68,0x1B,0x00},// ADI Required Write
    {0x68,0x45,0x04},// ADI Required Write
    {0x68,0x97,0xC0},// ADI Required Write
    {0x68,0x3E,0x69},// ADI Required Write
    {0x68,0x3F,0x46},// ADI Required Write
    {0x68,0x4E,0xFE},// ADI Required Write 
    {0x68,0x4F,0x08},//ADI Required Write
    {0x68,0x50,0x00},// ADI Required Write
    {0x68,0x57,0xA3},// ADI Required Write
    {0x68,0x58,0x07},// ADI Required Write
    {0x68,0x6F,0x08},// ADI Required Write
    {0x68,0x83,0xFC},// Enable clock terminators for port A & B 
    {0x68,0x84,0x03},// FP MODE
    {0x68,0x85,0x10},// ADI Required Write 
    {0x68,0x86,0x9B},// ADI Required Write 
    {0x68,0x89,0x03},// HF Gain
    {0x68,0x9B,0x03},// ADI Required Write
    {0x68,0x93,0x03},// ADI Required Write
    {0x68,0x5A,0x80},// ADI Required Write
    {0x68,0x9C,0x80},// ADI Required Write
    {0x68,0x9C,0xC0},// ADI Required Write
    {0x68,0x9C,0x00},// ADI Required Write

    PDF

  • 0
    •  Analog Employees 
    on Jun 11, 2021 12:42 PM in reply to kim0716

    Hi,

      MCU cannot get any data means, Please crosscheck your schematic with reference by make sure with reset and other pins which related to micrcontroller and ADV7619 are connected properly.

      Without MCU you can able to get the output by running the script in AVES tool, Below register configuration are missing from your text, you need to program the other maps by using IO map then only you can able to access the respective maps like HDMI DPLL etc.

      98 FF 80 ; I2C reset
      98 F4 80 ; CEC
      98 F5 7C ; INFOFRAME
      98 F8 4C ; DPLL
      98 F9 64 ; KSV
      98 FA 6C ; EDID
      98 FB 68 ; HDMI
      98 FD 44 ; CP

    Thanks,

    Poornima

  • As shown in the hardware schematic diagram provided earlier,only 16 wires and 1 clock wire are connected between the microcontroller and adv7619,and the other pins are not connected. (the reason is that the microcontroller we use only supports this connection method). Under this condition, when the Op_FORMAT_ SEL set to 0x80, and HDMI interface output signal 1920* 1080@60 to adv7619, the microcontroller can receive data from the pixel output pin, but when the HDMI interface output signal 3840* 2160@30    to adv7619, the microcontroller will not be able to receive data from the pixel output pin. At this time, I change Op_FORMAT_ SEL value to  0x54, because the actual connection of hardware pins in this mode does not matched to the described in the specification, so I do not know how to receive data from pixel output pin

  • 0
    •  Analog Employees 
    on Jun 15, 2021 9:37 AM in reply to kim0716

    Hi,

    Depending on the OP_FORMAT_SEL  the pin assignment of YCbCr and RGB  will vary So you need to configure the pixel port pins according to the output format select.

     When OP_FORMAT_SEL as 0x80 in that case some of the pixel port pins will be in the high impedance state so the same configuration you should not use for 0x54 If so you will not get the video output for 4K input. Please configure the pixel port pins accordingly then your Microcontroller can able to fetch the correct data from ADV7619.

    Also make sure with below register configuration in IO map for 4K input.

      0xBF[0] = 1 then CP Core is bypassed which is required for formats above 170Mhz.

    Thanks,

    Poornima