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ADV7181C IC Programming User guide

Hello,

Currently I am working on ADV7181C IC and the application is to receive PAL and STANAGRGB video data.

I have following queries regarding the same:-

1)In the data sheet it is mentioned as "Analog component YPrPb/RGB video formats with embedded synchronization or with separate HS, VS, or CS"
I am not able to find the register set details of ADV7181C.
If I need to set the ADV7181C IC to get the output with separate HS,VS or CS value then, which register I need to set.

2)In the ADV7181C data sheet, some of the details of the register configuration has been mentioned but the register address are not mentioned.
Can i get the programming user guide of ADV7181C IC or any software manual where I can find information about the register address and the data bit information.

Can you please share the information of ADV7181C IC register set address and its bits configuration details.

Thanks & Regards,
Arpitha

  • Hello,

    We are interfacing the ADV7181C IC with Xilinx Video In to AXI stream out IP.

    Here for this Video In to AXI Stream Out IP, the data valid signal is always required in order to generate the AXI stream out data.

    Since from ADV7181C IC ,the DE signal is muxed with field-id, and for interlaced video we need to connect the field id signal to the downstream IP.

    To generate the DE signal for the Video In to AXI Stream Out IP we need to write the custom logic (a glue logic interface between the ADV7181C IC and Video In to AXI Stream Out IP)

    It would be more helpful to us if we have any timing diagram of the output video data ,synchronization signal with field id and data enable which will help us to extract the DE signal for 720*576 @25i

    Or If you have already faced a issue like this with Xilinx IP than can you share any example design regarding the same.

    Thanks & Regards,

    Arpitha

  • Hi,

     Please note that DE is part of the input signaling and It can be re-generated from VS and HS if DE does not exist.  DE is an integral part of the HDMI stream.  

    Note: DE just signals active video.  VSync signals start of frame while HSync signals start of line.  Blanking lines will be started by HSync but have no DE or active video.  Video lines will be started by HSync, have a back porch delay and then DE goes high indicating the start of active video.

    Thanks,

    Poornima

  • Hello,

    Thank you for your constant support.

    This cleared my understanding regarding the DE signal

    One more doubt is :-

    Here in the ADV7181C Manual in page 6, it has been mentioned that the output from the CP can be programmed to get SDR 8-/10-bit 4:2:2 YCrCb for 525i, 625i but in the register CP output selection i.e.CPOP_SEL[0:3] which controls the format of the output data from the CP core, the register set value is not given for  SDR 8-/10-bit 4:2:2 YCrCb for 525i, 625i.

    Can I know where I can get that information.

    If our input is graphic mode RGB than, Will the CP output can be 8-bit 4:2:2 YCrCb fro 25i.

    Thanks,

    With Regards,

    Arpitha

  • Hi,

      If our input is graphic mode RGB than, Will the CP output can be 8-bit 4:2:2 YCrCb fro 525i.

         Yes, you can control the CPOP_SEL[0:3] register when your input is graphic mode.

      Please note that component processor (CP) section, which processes YPrPb and RGB component formats, including RGB graphics so you can configure CPOP_SEL[0:3] register for graphic input.

    Thanks,

    Poornima

  • Hello,

    Here, it is mentioned as SDR 8-10 bit YCrCb output

    For resolution 720*576 @ 25i (576i) can we get the output from CP as SDR 8-10 bit YCrCb output?

    But here  the configuration of register set for SDR 8-10 bit YCrCb output is not mentioned

    Thanks,

    With Regards,

    Arpitha

  • Hi,

      But here the configuration of register set for SDR 8-10 bit YCrCb output is not mentioned ?

         Yes You are right, In CPOP_SEL[0:3] register configuration, its mentioned only for 8/10 bit in DDR mode but not in SDR mode.

    Can you please try the configuration using OF_SEL[3:0] register in SDP map, Please refer below snap for your reference and let us know,

    Thanks,

    Poornima

  • Okay.

    Will try and update

    But if the input is RGB and output is YCrCb than the input data should pass through CSC which is enabled only in CP mode , so I had to select the CPOP_SEL register for output.

    Thanks,

    Arpitha

  • Hi,

      In script for 8 bit 422 SDR mode its configured like at ADV7181D_Evaluation_Software.zip

            42 6B 83 ; 422 8bit out
            42 C9 00 ; SDR mode
            42 52 00 ; Colour Space Conversion from RGB->YCrCb

    As per CPOP_SEL[0:3] register configuration,if it is 83 then it will be like 16bit output, So for 8 bit output we need to configure the pixel port in below pin assignment.

    8-bit out   YPrPb=P19-P12/P2-P9.

    16-bit out  Y= P19-P12

                        PrPb = P2-P9.

    Thanks,

    Poornima

  • Thank you,

    I will check it out

    Regards,

    Arpitha

  • Hello,

    When we connect the input to the decoder as RGB through Ain4,Ain5,Ain6 input of the decoder, then can we take the output from decoder as 8bit YCbCR 422 in BT656 format?

    Will the output from P19:P12 will be 8-bit Cr/Cb followed by Y in case of CP mode?

    Thanks,

    Arpitha