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ADV7181C IC Programming User guide

Hello,

Currently I am working on ADV7181C IC and the application is to receive PAL and STANAGRGB video data.

I have following queries regarding the same:-

1)In the data sheet it is mentioned as "Analog component YPrPb/RGB video formats with embedded synchronization or with separate HS, VS, or CS"
I am not able to find the register set details of ADV7181C.
If I need to set the ADV7181C IC to get the output with separate HS,VS or CS value then, which register I need to set.

2)In the ADV7181C data sheet, some of the details of the register configuration has been mentioned but the register address are not mentioned.
Can i get the programming user guide of ADV7181C IC or any software manual where I can find information about the register address and the data bit information.

Can you please share the information of ADV7181C IC register set address and its bits configuration details.

Thanks & Regards,
Arpitha

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  • Hi,

    Moving this to the Video applications community so they can further assist you.

    Regards,

    Andrei

  • Hi,

      1.  720*576@25i is a standard resolution So ADV7181C can support this format.

           For more details Please refer Page43 in ADV7181C_Manual_RevC.Pdf

      2.  LLC(Pixel clock) for 720*576@25i corresponds to 13.5Mhz.,Generally Pixel clock can be calculated using below formula,

            Pixel Clock = Horizontal total pixels * Vertical total pixels * vertical frequency
                                                      864*625*25 = 13.5Mhz

           Please refer CEA spec for format(Resolution) timing details.

     3. ADV7343 can support standard resolution of 720*576 @25i. Please refer Page5 in ADV7343 datasheet.

    Thanks,

    Poornima

  • Hello,

    In page 5 of ADV7343 datasheet , for resolution 720*576 @25i , there the input clock is given as 27MHz.

    and one more doubt ,if I need information of both DE and Field-id signal in case of input interlaced video than is it possible through any register set configuration. I have found that the register "F_OUT_SEL" is used to switch between the DE and field_id signal.

    But in case of the interlaced video input how the valid data is extracted when synchronization signals are used HS and VS pin

    Is there any way where i can extract information of both field_id and data enable and pass it to next downstream IP.

    Thanks,

    Arpitha

  • Hi,

     In page 5 of ADV7343 datasheet , for resolution 720*576 @25i , there the input clock is given as 27MHz.

           In Table1 of Page5 is the clock input of ADV734x via CLKIN pins.

          13.5Mhz is nothing but the pixel clock(LLC) for the particular format. This can be calculated by using above formula by considering the above parameters for particular format.

    F_OUT_SEL - This register is used to allows the switching of an active window output on the F pin

    So normally interlaced formats use VS, HS and Field only.  DE doesn't make sense since the active video width is different depending on odd/even field. So only progressive formats can really use DE.

    Interlaced mode :
       The even odd field information is included in embedded in the digital synchronization signals.
     It is also possible to use the VS/FIELD/SFL pin to determine even/odd fields.
     In this mode the VS/FIELD/SFL pin is programmed to output field synchronization pulses.

    Progressive mode:
        The field bit goes low and stays low in progressive mode. i.e. even/odd information is not sent in embedded digital synchronization signals.
        The field synchronization pin will go low and stay low in progressive mode. i.e. even/odd information is not over synchronization pins.

    Thanks,

    Poornima

  • Hello,

    We are interfacing the ADV7181C IC with Xilinx Video In to AXI stream out IP.

    Here for this Video In to AXI Stream Out IP, the data valid signal is always required in order to generate the AXI stream out data.

    Since from ADV7181C IC ,the DE signal is muxed with field-id, and for interlaced video we need to connect the field id signal to the downstream IP.

    To generate the DE signal for the Video In to AXI Stream Out IP we need to write the custom logic (a glue logic interface between the ADV7181C IC and Video In to AXI Stream Out IP)

    It would be more helpful to us if we have any timing diagram of the output video data ,synchronization signal with field id and data enable which will help us to extract the DE signal for 720*576 @25i

    Or If you have already faced a issue like this with Xilinx IP than can you share any example design regarding the same.

    Thanks & Regards,

    Arpitha

  • Hi,

     Please note that DE is part of the input signaling and It can be re-generated from VS and HS if DE does not exist.  DE is an integral part of the HDMI stream.  

    Note: DE just signals active video.  VSync signals start of frame while HSync signals start of line.  Blanking lines will be started by HSync but have no DE or active video.  Video lines will be started by HSync, have a back porch delay and then DE goes high indicating the start of active video.

    Thanks,

    Poornima

  • Hello,

    Thank you for your constant support.

    This cleared my understanding regarding the DE signal

    One more doubt is :-

    Here in the ADV7181C Manual in page 6, it has been mentioned that the output from the CP can be programmed to get SDR 8-/10-bit 4:2:2 YCrCb for 525i, 625i but in the register CP output selection i.e.CPOP_SEL[0:3] which controls the format of the output data from the CP core, the register set value is not given for  SDR 8-/10-bit 4:2:2 YCrCb for 525i, 625i.

    Can I know where I can get that information.

    If our input is graphic mode RGB than, Will the CP output can be 8-bit 4:2:2 YCrCb fro 25i.

    Thanks,

    With Regards,

    Arpitha

  • Hi,

      If our input is graphic mode RGB than, Will the CP output can be 8-bit 4:2:2 YCrCb fro 525i.

         Yes, you can control the CPOP_SEL[0:3] register when your input is graphic mode.

      Please note that component processor (CP) section, which processes YPrPb and RGB component formats, including RGB graphics so you can configure CPOP_SEL[0:3] register for graphic input.

    Thanks,

    Poornima

  • Hello,

    Here, it is mentioned as SDR 8-10 bit YCrCb output

    For resolution 720*576 @ 25i (576i) can we get the output from CP as SDR 8-10 bit YCrCb output?

    But here  the configuration of register set for SDR 8-10 bit YCrCb output is not mentioned

    Thanks,

    With Regards,

    Arpitha

  • Hi,

      But here the configuration of register set for SDR 8-10 bit YCrCb output is not mentioned ?

         Yes You are right, In CPOP_SEL[0:3] register configuration, its mentioned only for 8/10 bit in DDR mode but not in SDR mode.

    Can you please try the configuration using OF_SEL[3:0] register in SDP map, Please refer below snap for your reference and let us know,

    Thanks,

    Poornima

Reply
  • Hi,

      But here the configuration of register set for SDR 8-10 bit YCrCb output is not mentioned ?

         Yes You are right, In CPOP_SEL[0:3] register configuration, its mentioned only for 8/10 bit in DDR mode but not in SDR mode.

    Can you please try the configuration using OF_SEL[3:0] register in SDP map, Please refer below snap for your reference and let us know,

    Thanks,

    Poornima

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