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ADV7181C IC Programming User guide

Hello,

Currently I am working on ADV7181C IC and the application is to receive PAL and STANAGRGB video data.

I have following queries regarding the same:-

1)In the data sheet it is mentioned as "Analog component YPrPb/RGB video formats with embedded synchronization or with separate HS, VS, or CS"
I am not able to find the register set details of ADV7181C.
If I need to set the ADV7181C IC to get the output with separate HS,VS or CS value then, which register I need to set.

2)In the ADV7181C data sheet, some of the details of the register configuration has been mentioned but the register address are not mentioned.
Can i get the programming user guide of ADV7181C IC or any software manual where I can find information about the register address and the data bit information.

Can you please share the information of ADV7181C IC register set address and its bits configuration details.

Thanks & Regards,
Arpitha

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  • Hi,

    Moving this to the Video applications community so they can further assist you.

    Regards,

    Andrei

  • Hi,

      1. By using register 0x85(CP DETECTION CONTROL1),  you can take the sync signal output from HS, VS/CS pins. Please refer Page 236 in ADV7181C_Manual_RevC.pdf

    2. Please refer section 11.4 ( Pg 206- Table 59) to get the I2C register map and configuration details for different register address of ADV7181C at 0407.ADV7181C_Manuals.zip

    Also note that Depending upon the ALSB pin, we can select the I2C register address for ADV7181C.

       If ALSB pin is high, then the register address is 0x42.

       If ALSB pin is low,   then the register address is 0x40.

    Thanks,

    Poornima

  • Hello,

    Thank you for the support.

    I will go through the Manual.

    Thanks,

    Arpitha

  • Hi,

      Ok,Please let us know if any further issues.

    Thanks,

    Poornima

  • Hello,

    Currently I am working with ADV7181C and ADV7343 IC's

    Following are the queries regarding the IC:-

    1) Is 720*576 @25i and 720*575 @25i  are the standard resolution supported by ADV7181C ? Because I couldn't find it in the ADV7181C Manual data sheet.

    2) Will the LLC frequency for the above mentioned resolution will be 27MHz or 13.5MHz or 54MHz? Can I know how the LLC frequency is decided and configured.

    3)Is 720*576 @25i and 720*575 @25i are the standard resolution supported by ADV7343 IC ?Because I couldn't find it in the ADV7343 data sheet.

    Thanks,

    Arpitha

  • Hi,

      1.  720*576@25i is a standard resolution So ADV7181C can support this format.

           For more details Please refer Page43 in ADV7181C_Manual_RevC.Pdf

      2.  LLC(Pixel clock) for 720*576@25i corresponds to 13.5Mhz.,Generally Pixel clock can be calculated using below formula,

            Pixel Clock = Horizontal total pixels * Vertical total pixels * vertical frequency
                                                      864*625*25 = 13.5Mhz

           Please refer CEA spec for format(Resolution) timing details.

     3. ADV7343 can support standard resolution of 720*576 @25i. Please refer Page5 in ADV7343 datasheet.

    Thanks,

    Poornima

  • Hello,

    In page 5 of ADV7343 datasheet , for resolution 720*576 @25i , there the input clock is given as 27MHz.

    and one more doubt ,if I need information of both DE and Field-id signal in case of input interlaced video than is it possible through any register set configuration. I have found that the register "F_OUT_SEL" is used to switch between the DE and field_id signal.

    But in case of the interlaced video input how the valid data is extracted when synchronization signals are used HS and VS pin

    Is there any way where i can extract information of both field_id and data enable and pass it to next downstream IP.

    Thanks,

    Arpitha

  • Hi,

     In page 5 of ADV7343 datasheet , for resolution 720*576 @25i , there the input clock is given as 27MHz.

           In Table1 of Page5 is the clock input of ADV734x via CLKIN pins.

          13.5Mhz is nothing but the pixel clock(LLC) for the particular format. This can be calculated by using above formula by considering the above parameters for particular format.

    F_OUT_SEL - This register is used to allows the switching of an active window output on the F pin

    So normally interlaced formats use VS, HS and Field only.  DE doesn't make sense since the active video width is different depending on odd/even field. So only progressive formats can really use DE.

    Interlaced mode :
       The even odd field information is included in embedded in the digital synchronization signals.
     It is also possible to use the VS/FIELD/SFL pin to determine even/odd fields.
     In this mode the VS/FIELD/SFL pin is programmed to output field synchronization pulses.

    Progressive mode:
        The field bit goes low and stays low in progressive mode. i.e. even/odd information is not sent in embedded digital synchronization signals.
        The field synchronization pin will go low and stay low in progressive mode. i.e. even/odd information is not over synchronization pins.

    Thanks,

    Poornima

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