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ADV7343 TEST PATTERN GENERATION

Hi team,

We are using encoder ADV7343 in our project. We are providing 27MHz clock to CLKIN_A. 

Following register configurations are performed:

0x17  - 0x02

0x00 - 0xFC

0x82 - 0xC9

0x84 - 0x40

0x11 - 0x80

0x8C - 0xCB

0x8D - 0x8A

0x8E - 0x09

0x8F - 0x2A

As per the datasheet, for the above settings, we should be able to see the test pattern on DACs. But we are not obtaining any test pattern from DACs. 

Is there any other settings apart from these in order to obtain test pattern in SD mode?

Thanks in advance.

With regards,

Madhuri C N.

  • Hi,

       Please let us know, whether you are generating the test pattern for PAL or NTSC.

       If is an PAL test pattern, Please make sure with below register settings,

         0x17  - 0x02

        0x00 - 0xFC

        0x82 - 0xC9

        0x84 - 0x40

        0x80 - 0x11

        0x8C - 0xCB

        0x8D - 0x8A

        0x8E - 0x09

        0x8F - 0x2A

    If it is an NTSC color test pattern, Please make sure with below register settings,

        0x17  - 0x02

        0x00 - 0xFC

        0x82 - 0xC9

    Thanks,

    Poornima

  • Hi team,

    We have configured the registers which are mentioned above for both PAL and NTSC formats. We have confirmed the register configuration by probing SDA and SCLK lines( image is attached below for probed signals) on encoder and through console. Obtained log file is attached below.

    Regards,

    Madhuri C N

    PAL CONFIGURATION FOR ADV7343
    -----------------------------
    
    [Thu Apr 29 09:55:15.880 2021] Configuring ADV7343 for test pattern generation (PAL)
    [Thu Apr 29 09:55:15.886 2021] 
    [Thu Apr 29 09:55:15.886 2021] main: I2C_Init() completed for ADV7343
    [Thu Apr 29 09:55:15.893 2021] main: I2C_Init() completed for 2nd ADV7181
    [Thu Apr 29 09:55:15.930 2021] testPatternGeneration: ADV7343 initialization complete. Configuring...
    [Thu Apr 29 09:55:15.941 2021] testPatternGeneration: (17) = 0
    [Thu Apr 29 09:55:15.942 2021] 
    [Thu Apr 29 09:55:15.942 2021] testPatternGeneration: (0) = fc
    [Thu Apr 29 09:55:15.950 2021] 
    [Thu Apr 29 09:55:15.950 2021] testPatternGeneration: (82) = c9
    [Thu Apr 29 09:55:15.950 2021] 
    [Thu Apr 29 09:55:15.950 2021] testPatternGeneration: (84) = 40
    [Thu Apr 29 09:55:15.956 2021] 
    [Thu Apr 29 09:55:15.956 2021] testPatternGeneration: (80) = 11
    [Thu Apr 29 09:55:15.962 2021] 
    [Thu Apr 29 09:55:15.962 2021] testPatternGeneration: (8c) = cb
    [Thu Apr 29 09:55:15.962 2021] 
    [Thu Apr 29 09:55:15.962 2021] testPatternGeneration: (8d) = 8a
    [Thu Apr 29 09:55:15.970 2021] 
    [Thu Apr 29 09:55:15.970 2021] testPatternGeneration: (8e) = 9
    [Thu Apr 29 09:55:15.970 2021] 
    [Thu Apr 29 09:55:15.970 2021] testPatternGeneration: (8f) = 2a
    [Thu Apr 29 09:55:15.975 2021] 
    [Thu Apr 29 09:55:15.975 2021] main: testPatternGeneration configuration complete
    
    -----------------------------------------------------------------------------------------------------------------------------
    
    NTSC CONFIGURATION FOR ADV7343
    ------------------------------
    
    [Thu Apr 29 10:02:22.019 2021] Configuring ADV7343 for test pattern generation (NTSC)
    [Thu Apr 29 10:02:22.030 2021] 
    [Thu Apr 29 10:02:22.030 2021] main: I2C_Init() completed for ADV7343
    [Thu Apr 29 10:02:22.036 2021] main: I2C_Init() completed for 2nd ADV7181
    [Thu Apr 29 10:02:22.069 2021] testPatternGeneration: ADV7343 initialization complete. Configuring...
    [Thu Apr 29 10:02:22.080 2021] testPatternGeneration: (17) = 0
    [Thu Apr 29 10:02:22.082 2021] 
    [Thu Apr 29 10:02:22.082 2021] testPatternGeneration: (0) = fc
    [Thu Apr 29 10:02:22.095 2021] 
    [Thu Apr 29 10:02:22.095 2021] testPatternGeneration: (82) = cb
    [Thu Apr 29 10:02:22.102 2021] 
    [Thu Apr 29 10:02:22.102 2021] testPatternGeneration: (84) = 40
    [Thu Apr 29 10:02:22.102 2021] 
    [Thu Apr 29 10:02:22.102 2021] main: testPatternGeneration configuration complete
    

  • With reference to above observations, test pattern is not generated on DAC outputs of encoder ADV7343. Thanks in advance.

    Regards,

    Madhuri C N

  • Hi,

      Please note that CVBS output is available on DAC 4, S-Video (Y-C) output is on DAC 5 and DAC 6, and YPrPb output is on DAC 1 to DAC 3. So you should configure 0x82 register as 0xC9 but you have configured it as 0xCB. Please refer Table37 in ADV734x datasheet.

      Also you have not enabled the software reset in the register 0x17

      But before doing any I2C configuration we need to reset all registers to their default values. So please configure 0x17 as 0x02.

    Thanks,

    Poornima