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(ADV7480)Can we control LP⇔HS mode using  CSITX_PWRDN bit ?

Hi !

I was reading AN-1337.

At the application note , this is written.

Does this mean CSITX_PWRDN can control which mode ADV7480 outputs?

I mean LS mode or HS mode.

I want to no this because there is no explanation at the manual.

Also our customer are using SoC and after they set SoC , SoC will check that MIPI-TX is LP-mode immediately.

And if MIPI-TX is not LP-mode , SoC will be error status.

So they want to know how to set LP-mode.

Best regards

Kawa

  • Hi Mike!

    Thank you for your reply.

    I have to make sure what my customer want to know.

    As I wrote , SoC is checking that MIPI-TX is LP mode or not.

    Not waiting LP-HS transition.

    And at AN-1337, this is written.

    *****************************************************************************

    To overcome this issue, manually program the clock lane of the
    ADV7280-M, ADV7281-M, ADV7281-MA, or ADV7282-M to
    enter and then exit LP mode. The easiest way to do this is by
    toggling the CSITX_PWRDN bit (Address 0x00, Bit 7).

    *****************************************************************************

    And I think ADV7480 is same as ADV728x.

    So I thought CSITX_PWRDN bit can toggle LP-HS transition.

    Isn't it ?

    Best regards

    Kawa

  • Hi,

    Your question has been forwarded to the part specialist

    Best Regards,

    Jeyasudha.M

  • If the Start up sequence is followed (and the SOC is configured before the end of the sequence or ideally even before the start) then the SOC will see a compliant LP - HS state transition.

    The CSITX_PWRD bit is the powerdownfor the Tx logic block. It does not transfer directly over to controlling LP or HS state on the MIPI outputs.

    Like mentioned in a separate thread when the   CSITX_PWRD bit is used to disable the Tx, the outputs will not immediately go into LP state. The transmitter will finish out the current video line.

    When the CSITX_PWRD bit is used to enable the Tx its does not start transmitting straight away as the clock line is held static and only released later with i2c writes. This is to ensure there is a compliant LP - HS transition.

    Mike

  • Hi Mike

    Thank you for your reply.
    I understood what you said.

    Your answer was perfect for me.

    I will try to explain this to my customer.

    Thanks again.

    Best regards

    Kawa

  • Hi Kawa,

    Yes the CSITX_PWRDN bit will power up or down the Tx and this roughly equates to enabling or disabling the clock lane.

    But it is not as simple as the CSITX_PWRDN bit toggling a LP-HS transition directly.

    In the case of LP state initially, when the CSITX_PWRD bit is used to enable the Tx its does not start transmitting straight away as the clock line is held static and only released later with i2c writes. This is to ensure there is a compliant LP - HS transition.

    Likewise when CSITX_PWRD bit is used to disable the Tx, the outputs will not immediately go into LP state from HS. The transmitter will finish out the current video line.

    So yes you can more or less force LP or LP-HS transition by just toggling the CSITX_PWRDN bit but for a fully MIPI standard compliant LP-HS transition you would need to sequence the CSITX_PWRDN with the control of the clock lane output as the scripts do.

    Regards,

    Mike