missing green component in adv7181d

I am using the AD7181 in graphics mode. Output is 16bit SDR YPRPB, with AV codes inserted. Input is R on AIN5, G on AIN2, B on AIN3. Separate H & V in. A typical VGA input, 1024x768/60hz.

I have 2 chips at I2C addresses 0x20 and 0x21. Clock is 28.63636. My problem is that the green component seems to be missing. For example, white content comes out as magenta. Can you verify my configuration?

Thanks

Regards, Brian

 

My configuration script (typical uboot syntax: write, chip address, register.number of bytes, write data):

i2c mw 20 00.1 1b # cvbs on ain1

i2c mw 21 00.1 1b # cvbs on ain1

i2c mw 20 05.1 02 # set to graphix

i2c mw 21 05.1 02 # set to graphix

i2c mw 20 06.1 0c # set to xga

i2c mw 21 06.1 0c # set to xga

i2c mw 20 0f.1 02 # shutoff fb

i2c mw 21 0f.1 02

i2c mw 20 13.1 04 # ext clk

i2c mw 21 13.1 04 # ext clk

i2c mw 20 c3.1 31 # set r to ain5 g to ain 2

i2c mw 21 c3.1 31 # as above for other chip

i2c mw 20 c4.1 c2 # set b to ain 3

i2c mw 21 c4.1 c2 # as above for other chip

i2c mw 20 6b.1 c3 # set output fmt

i2c mw 21 6b.1 c3 # same for other chip

#i2c mw 20 73.1 df # gain

#i2c mw 21 73.1 df

#i2c mw 20 74.1 f7

#i2c mw 21 74.1 f7

#i2c mw 20 75.1 fd

#i2c mw 21 75.1 fd

#i2c mw 20 76.1 ff

#i2c mw 21 76.1 ff

i2c mw 20 77.1 04 # offset

i2c mw 21 77.1 04

i2c mw 20 78.1 08

i2c mw 21 78.1 08

i2c mw 20 79.1 02

i2c mw 21 79.1 02

i2c mw 20 7a.1 00

i2c mw 21 7a.1 00

i2c mw 20 7b.1 1f # set blank level

i2c mw 21 7b.1 1f # set blank levl

#i2c mw 20 85.1 0a #sync on sep h/v

#i2c mw 21 85.1 0a #sep hv sync

i2c mw 20 f4.1 3f # drv str

i2c mw 21 f4.1 3f # drv str

i2c mw 20 3a.1 20 # clk range

i2c mw 21 3a.1 20 # clk range

i2c mw 20 3c.1 5d # pump curr

i2c mw 21 3c.1 5d

i2c mw 20 03.1 09 # set pixel format, untristate outputs of ch1 7181

i2c mw 20 1d.1 40 # untristate llc ch1 7181

i2c mw 21 03.1 09 # set pixel format, untristate outputs of ch2 7181

i2c mw 21 1d.1 40 # untristate llc ch2 7181

  • 0
    •  Analog Employees 
    on Mar 30, 2021 1:22 PM

    Hi,

      Please crosscheck your I2C configuration with reference script which is available for the format - 1024x768/60hz( ##CP XGA 1024x768##) at 6545.ADV7181D_Evaluation_Software.zip

      Also try to configure the register CPOP_SEL[3:0] (CP), Address 0x6B[3:0] for 16bit SDR YPbPr output from the CP core. Refer Table52/82 in 'ADV7181D_Manual_Rev0.pdf'.

    Thanks,

    Poornima

  • Hi. I checked 0x6b, its correct for 16bit sdr yuv out from CP core. I looked at the reference script for CP XGA, is that for one of your eval boards? Not all of those setting match my use case but I'll check the video settings I think might help. thanks

    Brian

  • Poornima, I looked over your script for CP XGA 1024x768 from your zipfile. It has a few discrepancies. In the section I've attached below, register settings are made for addresses 0E and 52 which are changed a few lines later. It's also not for my use case, but I think I can ignore the settings that don't apply to me.  Please correct the discrepancies, otherwise I cannot trust that this script will work.

    42 0E 80 ; ADI Recommended Setting
    42 52 46 ; ADI Recommended Setting
    42 54 80 ; ADI Recommended Setting
    42 F6 3B ; ADI Recommended Setting
    42 0E 00 ; ADI Recommended Setting
    42 52 80 ; ADI Recommended Setting

  • 0
    •  Analog Employees 
    on Apr 8, 2021 1:16 PM in reply to bcmoore001

    Hi,

     These writes(ADI recommended writes) as non user adjustments and hence their function is not documented.              

    42 0E register writes are used for enabling the ADC's.Please refer below,

    42 0E 80 - ADI required write  (Enable ADC1)
    42 55 81 - ADI required write  (Enable ADC2)
    42 0E 00 - ADI required write  (Enable ADC3)

    42 52 register writes influences the bias current for the analog front end(AFE. This is the latest recommended write for new product designs to offer optimal performance.
    This write should not be performed for S-Video(YC) or component (YPbPr) inputs.

    42 52 80- Recommended AFE IBIAS Setting for CVBS mode of the ADV7180 in CVBS mode.

    Note: ADI recommended registers: These "ADI recommended write" register sequence should be followed w.r.t sample script.
    If those writes are not included, the part would not expect to work reliably (unless those values are default anyway).Those registers are generally internal settings that let us handle process variation which is why they are determined during characterization. The settings that show up as "ADI Recommended Settings" are the values that work reliably across voltage and temperature. They really should be called "ADI Required settings.

    Thanks,

    Poornima

  • Poornima, I have Rev0 of the user manual (not the datasheet) for this part. It is from 2011. That is ANCIENT! I could not locate an updated manual on your site, or any manual for that matter. Is there an updated manual, perhaps one that describes your "ADI recommended/required settings" in more detail? That info is missing from my manual. The register addresses 0x52 thru 0x55 are for CSC coefficients in my manual, not ADC settings. Is this an error in the manual? BTW what is the "42" and the "72" in your script? Are these addresses of some parts? My 7181 has an address of 0x20 or 21 depending on which way the I2C address LSB pin is pulled.

    Regards, Brian