Getting black pixels on the right and the left of image on ADV7180 output

Hello,

we use an ADV7180 for getting digital image from analog PAL source (monochrome images). Test source is a Teletest Pro OZT1200 box, providing a video pattern with a grid.

Expecting digital format is 576 lines x 720 pixels. Image seems correctly received but we have a few unexpected constant black pixels (8bit hexa value near 10) on the left (6 pixels) and on the right (3 pixels). You can see the received image below, with vertical black bars on the left and right (areas have been red outlined by myself)

If we select a fully white image as source pattern, the pb is the same (still have the same nb of black pixels on the left and on the right of received image).

We have made a record of the source signal and the measured durations are always

for 1 video line = 64us

for active part in a single video line = 52.6us

for horizontal synchro part in a single video line = 11.4us

Could it be possible that the black pixels received on the left and right are part of the horinzontal synchro considered as active video part when converting ?

Also, as we use the ADV7180 without modifying default register values (the only command sent on i2c to ADV7180 is for selecting input in register 00 when starting video acquisition), could you tell me if this pb could come from a wrong setting of ADV7180 ? I have found in a document ADV7180 - Preliminary register settings recommandations Rev. PrA an example of CVBS autodetect script with many more i2c commands than perfomed by our application but I am a newcomer in video acquisition and do not understand if listed operations are useful for our acquisition process.

Thank you for your help.

Parents
  • +1
    •  Analog Employees 
    on Mar 23, 2021 2:50 PM

    Hi,

     Please make sure whether you are using PAL? Generally for NTSC input these black video being output at the left/Right of the screen.

     Also make sure with crystal clock (i.e) you are providing correct XTAL 28.6363,and your script selects 28.63636 crystal.

    Thanks,

    Poornima

  • Hello Poornima,

    thank you for this elements. Here are the checks made after your remarks about possible cause.

    For the video test box Teletest Pro OZT1200, its output is only CVBS PAL 1Vp-p, 75ohm, so no way to erroneously get a NTSC image (see https://www.teletest.tv/store/p4/Video_and_stereo_audio_test_generator_TELETEST_PRO.html).

    For the clock source XTAL, we use a TXC AM-28.63636MAGK-T, in a way that seems compliant with suggested arrangement of page 111 of ADV7180 datasheet (Rev J) = crystal close and on the same side of the PCB as ADV7180, with an expected capacitor loading value of 12pF (according to TXC), modified into 20pF after application of Analog Devices application note AN-1260.

    For the script, we do not write into register with address x1D, and ADV7180 indicates the default loaded value is right for selecting 28MHz external crystal

    So the problem seems to come from somewhere else. Could it come from another register setting ? As I said, our script only writes into register 0x00 for selecting active input channel, nothing else, all the others registers are left with default values.

    Thanks

  • Hello Poormina,

    when you ask me to "check with other sources also", do you mean to set register 0x84 with values 0x01, 0x10 and 0x11 ? I should be able to run it this afternoon, so you will have it tomorrow.

  • 0
    •  Analog Employees 
    on Mar 30, 2021 12:32 PM in reply to expleo_tcou31

    Hi,

      If possible, Please share your register dump.

      We will crosscheck your I2C configuration from our end.

    Thanks,

    Poornima

  • Hello,

    we have tried setting register 0x84 with value 0x00, but no change observed (not worst, not better, black pixels on right/left still here).

    Here is the register dump made at init time (before selecting the active channel, no video signal injected).

    PDF

    We did not check yet these values with default values declared in ADV7180 datasheet, they should be found because we do not set any register before running. Our running sequence is : start ADV7180 without video input (no channel connected to video source), then (about 1 min later) connect the video source to any channel between 1 to 5 and set register 0x00 for selecting the channel with video source connected.

    An idea comes about clamp operation : when we start running by selecting the channel with video input, we do not make a reset for clamping circuitry (register 0x14), could it be a problem ?

    Thanksfor your help.

  • 0
    •  Analog Employees 
    on Apr 1, 2021 1:51 PM in reply to expleo_tcou31

    Hi,

     Please make sure your configuration with reference script since some configuration different from the reference one mainly the difference in sub address map.

    Also try configuring the HS/VS position control registers in Page91 of ADV7180 datasheet.

    Please note the Possible causes:

    - incorrect capture in the downstream device - incorrect timing/start of active video.

    - Incorrect analog image from source e.g. Camera itself. 

    ADV7180 does not use frame memory, so an image cannot be stored. If there are issues with the output timing/ alignment, the image would have some black (non-active) video on the left or right

    Thanks,

    Poornima

  • Hi Poornima,

    downstream device (FPGA) does not use HSYNC signal, only referring to values received on the digital bus for detecting start of active video according to BT656. Simulating it using a test bench allows to rely on a correct transmission of 720 active video pixel values if input sequence is in line with figure 37 of ADV7180 revJ datasheet.

    but as we were not sure about the meaning of the registers for ADV7180 itself (is its behaviour modified not only for the setting of HSYNC output ?) we have run a software release including a write operation in registers 0x35/0x36. As we had a 6 pixels wide balck strip on the left, we decided to add 6x2=12 clock pulse in the registers (so 14 for 0x35 instead of default 2 and 12 for 0x36 instead of default 0). But this has not changed the result displayed.

    We also ran a software release with a "reset clamping circuitry" (programming 0x30 in register 0x14) after the selection of input channel in register 0x0, but no change observed.

    perhaps it comes from source itself though when connecting the source directly on a monitor with PAL analog input, it seems not displaying this black strip on the left of image, but not sure that the monitor, which is a numerical device, does not perform something inside that removes the far left/far right parts of the image and masks the source issue.

    The problem is still not fully assigned to a part of the design.

    Thanks,

Reply
  • Hi Poornima,

    downstream device (FPGA) does not use HSYNC signal, only referring to values received on the digital bus for detecting start of active video according to BT656. Simulating it using a test bench allows to rely on a correct transmission of 720 active video pixel values if input sequence is in line with figure 37 of ADV7180 revJ datasheet.

    but as we were not sure about the meaning of the registers for ADV7180 itself (is its behaviour modified not only for the setting of HSYNC output ?) we have run a software release including a write operation in registers 0x35/0x36. As we had a 6 pixels wide balck strip on the left, we decided to add 6x2=12 clock pulse in the registers (so 14 for 0x35 instead of default 2 and 12 for 0x36 instead of default 0). But this has not changed the result displayed.

    We also ran a software release with a "reset clamping circuitry" (programming 0x30 in register 0x14) after the selection of input channel in register 0x0, but no change observed.

    perhaps it comes from source itself though when connecting the source directly on a monitor with PAL analog input, it seems not displaying this black strip on the left of image, but not sure that the monitor, which is a numerical device, does not perform something inside that removes the far left/far right parts of the image and masks the source issue.

    The problem is still not fully assigned to a part of the design.

    Thanks,

Children
  • 0
    •  Analog Employees 
    on Apr 20, 2021 1:40 PM in reply to expleo_tcou31

    Hi,

    Please make sure with below thing,

     Normally sinks would expect the correct timing. It depends on how the sink interprets the incoming timing.  If the sink thinks the Hsync back porch is only 10 pixels wide and the source is outputting a back porch of 100 pixels then we will get a 90 pixel black bar on the left side of the screen.

    So we need to look at the timing on a scope and try to match it to a timing the sink is expecting.

    Thanks,

    Poornima

  • Hi Poornima,

    In our design, the downstream FPGA device receives the digital values from the ADV7180 (clocked by LLC output signal of ADV7180) and wait until getting the SAV code FF00 0080 (StartActiveVideo for odd line) or FF00 00C7 (StartActiveVideo for even line), no duration is expected from EAV (EndActiveVideo) of previous line. The number of pixels corresponding to the horizontal blanking may be 10 or 100, I think it does not matter for it. Then once SAV code is received, the downstream FPGA device considers pixels are for active video until getting any EAV code FF00 009D (all odd lines but the last) or FF00 00B6 (last odd line) or FF00 00DA (all even lines but the last) or FF00 00F1 (last even line), and the duration of active video is expected to be 720 pixels long.

    When we get black pixels on the left side of image, it means that first pixel values received after SAV code are always low values, even if video line is a full white line as in following example of source signal.

    scope screen for source signal is given below, with correct duration found for 1 video line = 64us, and measured duration for  horizontal synchro part in a single video line = 11.4us / active part in a single video line = 52.6us

    the question could be Are we sure the ADV7180 gives 720 pixels when active video line is 52.6us long ? Is it ok to compute that with a 27MHz clock, it gives 1420 samples, so using 2 samples (MSB+LSB) for 1 pixel, it gives only 710 pixels, not 720 ? and missing pixels could be the black stripes on the left and the right, which are (6+3)=9 pixels, nearly matching the missing number of samples ?

  • 0
    •  Analog Employees 
    on Apr 26, 2021 5:45 AM in reply to expleo_tcou31

    Hi,

      When there is an input, the sync settings are passed through. It's not uncommon for sources to vary a few lines but 10 is kind of unusual. The ADV7180 can't change the sync signals so that's likely how it's coming from the source-- you can try a few different sources to see the variance.

      Please note that ADV7180 has no memory and can't retime the signals-- it can't add or remove lines.  If 10 lines were actually lost then the pixel clock should be different as well as the H sync.

    It's physically impossible for the ADV7180 to add or remove lines.  That would require memory which the part doesn't have and the timing would change. if you are seeing more blanking lines when you see the fewer active lines.

    So the issue has to do be with the the sync signals/timing codes. Please try with below configuration to adjust the timing

     When NEWAVMODE is 0, EAV/SAV codes are generated to suit Analog Devices encoders. No adjustments are possible.

     When NEWAVMODE is 1(default), it enables the manual position of the VSYNC, FIELD, and AV codes using Register 0x32 to Register 0x33 and Register 0xE5 to Register 0xEA. Refer Page 48 in ADV7180 datasheet.

    Thanks,

    Poornima

  • Hi Poornima,

    Thank you for your answer, but I do not understand why you explain about lost lines, it seems I should have not been clear in my previous message about our problem, there is not any lost lines in the data received from ADV7180, only black pixels on the left (6 pixels) and on the right (3 pixels) of the image.

    I confirm NEWAVEMODE is 1 in (register 0x31 read with value set to 0x12), but I do not understand how Vertical Sync signal is linked to our problem, which seems to be much more a pb of Horizontal sync vs Active video. Did I misunderstand something ? 

    And you did not answer to the question about pixel numbers delivered by ADV7180 for Active Video part in a line : are we sure it gives 720 pixels (= 1440 samples) even if duration of Active Video is 52.6 us long (instead of 53.35 us required for getting 1440 samples with a 27 MHz clock) ?

  • 0
    •  Analog Employees 
    on Apr 28, 2021 5:24 PM in reply to expleo_tcou31

    Hi,

      Please configure the register according to the Table 66 for PAL in ADV7180 datasheet and let us know the result.

      Please note that If the part really is putting out black frames, you should be able to see it on the bus and you probably should see some glitches on the VCLK/HSYNC/VSYNC.  That would be a good indication that the PLL lost lock So let us know whether you are facing this behavior with ADV7180 output pins.

      Also there are several reasons that could happen but the most common ones would be layout related on the TMDS line from the connector to the ADV7180 or power/GND issues.

    ---> (instead of 53.35 us required for getting 1440 samples with a 27 MHz clock) ?

         Yes, If your input is 720(1440) x 576i@50 then the pixel clock would be 27Mhz only.

    ---> I confirm NEWAVEMODE is 1 in (register 0x31 read with value set to 0x12), but I do not understand how Vertical Sync signal is linked to our problem, which seems to be much more a pb of Horizontal sync vs Active video. Did I misunderstand something ? 

        You are getting the black pixels on the right and left side of the image and it corresponds to Vsync period, this is the reason we have suggested to adjust the VS/FIELD related register. Please refer below image

    Thanks,

    Poornima