ADV7181D SVGA(800*600) @60Hz Image shift

Our system use ADV7181D for RGB Graphics Processing that SVGA to 12bit 4:4:4 RGB DDR.

The problem is Image shift to right.

I think that DE(Data Enable) and Pixel Data are out of alighment.

Please tell me how to set the position and width of DE(Data Enable).

  • 0
    •  Analog Employees 
    on Feb 26, 2021 10:32 AM 1 month ago

    Hi,

    Please make sure the shift is occurring in the backend device(s).
    Do you see the shift at the output of the ADV7181D?

    Please try adjusting the following controls to adjust the shift,

    START_HS[9:0] - Address 0x7C and 0x7E, [3:2] and [7:0]

    END_HS[9:0] - Address 0x7C and Address 0x7D, [1:0] and [7:0]

    START_VS[3:0] - Address 0x7F, [3:0]

    END_VS[3:0] - Address 0x7F, [7:4]

    START_FE[3:0] (Start Field Even) - Address 0x80, [7:4]

    START_FO[3:0] (Start Field Odd) - Address 0x80, [3:0]

    PIN_IN_HS - Address 0x7C, [7]

    PIN_INV_VS - Address 0x7C, [6]

    PIN_INV_F - Address 0x7C, [5]

    These controls are described in Section7.13 in the hardware manual available at ADV7181D Design Support Files .

    Thanks,

    Poornima

  • Dear Poornima

    Thank you for your replay.

    I will try your advice.

    Best regards.

    KNAGATA

  • Dear Poornima and All.

    There is no description in the hardware manual about how to set the position and width of DE(Data Enable).

    Can anyone tell me the link between HS, VS and FIELD for DE?

    Best regards.

    KNAGATA

  • 0
    •  Analog Employees 
    on Mar 1, 2021 11:44 AM 1 month ago in reply to KNAGATA

    Hi,

     Please let us know, Have you referred the section 7.13 in the attached document ADV7181D_Manuals.zip

     Can anyone tell me the link between HS, VS and FIELD for DE?

       Normally HS timing is based on a pixel clock count, VS, DE and FIELD are based on the HS counts.  FIELD and DE existence are based on the format, FIELD delineates the odd and even fields of a frame in interlaced formats and DE defines the active video in progressive formats.

      Field only has meaning for interlaced video.  You can derive Field from VS and HS if needed. Progressive requires VS and HS.

    Note:  DE is derived from Hsync and Vsync.  Embedded syncs only contain H, V and Field information, no DE therefore DE would be derived from H & V. 

    Thanks,

    Poornima

  • Dear Poornima

    Thank you for your replay.

    Yes, I have referred the section 7.13 in the  hardware manual.

    By the way, is the position and width of DE synchronized with that of HS and VS?

    Normally, I think the width of DE is wider than that of HS and VS.

    I want to know specifically how DE is generated from HS and VS.

    Best regards.

    KNAGATA