configuration for ADV7182A using FPGA via I2C

Hi all,

My project structure is VIDEO -> ADV7182A -> FPGA -> PC. I got EVAL-ADV7182AEBZ evaluation board and i used it to show video on montitor

Now i want to use only ADV7182A because i just need 8 pixel port and LLC clock.

I have configured ADV7182A  to use FPGA over the I2Cprotocol according to this

##02_CVBS SINGLE ENDED AUTODETECT ##

:Autodetect CVBS Single Ended In Ain 1, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7182
delay 10 ; Wait 10ms
42 0F 00 ; Exit Power Down Mode [ADV7182A writes begin]
42 52 CD ; SE_CVBS AFE IBIAS
42 00 00 ; CVBS in on AIN1
42 0E 80 ; ADI Required Write
42 9C 00 ; Reset Current Clamp Circuitry [step1]
42 9C FF ; Reset Current Clamp Circuitry [step2]
42 0E 00 ; Enter User Sub Map
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7182A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver [ADV7182A writes finished]
End

I have a problem that the image is not displayed as expected.(I got 27Mhz LLC clock and 28.63636 Mhz Crystal)

The picture below is not showing as expected. Rather, it doesn't show that many vertical black stripes.

Has anyone seen this problem??

Thanks!

Parents
  • 0
    •  Analog Employees 
    on Feb 24, 2021 1:13 PM

    Hi,

          Please try with different source and sink.  Some monitors will scale the incoming video to it's native resolution.  As an example suppose I have a monitor with native resolution of 1080p and the incoming stream is VGA60.  It will scale it up to 1080p to match the monitor.  This scaling can cause pixel by pixel distortion.
     Make sure the monitor is not in some sort of zoom mode and distorting the true image.     

        Also make sure with the chip power supplies are clean and well decoupled and make sure there is no noise getting injected into the ADC section of the chip.

    Thanks,

    Poornima

  • Hi PoornimaSubramani,

    Thanks for your help.

    I have followed your opinion. I have changed anotherPC, another monitor but nothing has changed. 

    I have checked power supply. Distance from ADV to FPGA is short and the layout is good enough to avoid noise.

    Do you have any idea?

    Thanks,

    L V

  • 0
    •  Analog Employees 
    on Mar 5, 2021 2:45 PM in reply to L V

    Hi,

     Please let us know the configuration for free run mode?

     If free run means you should not give the input from the source, the ADV7182A will output the default color pattern when source is not connected.

     Also let us know, How you are running the I2C script?

    Thanks,

    Poornima

  • I followed this script for the free run mode and I got the same error.

    delay 10 ; Wait 10ms After Hardware Reset To Start I2C
    42 0F 80 ; Reset ADV7182
    delay 10 ; Wait 10ms
    42 0F 00 ; Exit Power Down Mode [ADV7182A writes begin]
    42 52 CD ; AFE IBIAS
    42 00 05 ; INSEL = unconnected input
    42 0C 37 ; Force Free run mode [Free run]
    42 14 11 ; Set Free-run pattern to 100% color bars [Free run]
    42 02 54 ; Force standard to NTSC-M [Free run]
    42 17 41 ; Enable SH1
    42 03 0C ; Enable Pixel & Sync output drivers
    42 04 07 ; Power-up INTRQ, HS & VS pads
    42 13 00 ; Enable ADV7182A for 28_63636MHz crystal
    42 1D 40 ; Enable LLC output driver [ADV7182A writes finished]
    End

    And i used the state machine in VHDL to run the script. Each command I put in a state machine. I checked I recorded the values in the registers as correct.

    So what can i do?

    I just need to use ADV7182 in mode CVBS SINGLE ENDED AUTODETECT Ain1??

    And why the EVAL-ADV7182AEBZ command to read data immidiately after command to write as below?

    drive.google.com/.../view

    Thanks!

    L V

  • 0
    •  Analog Employees 
    on Mar 8, 2021 1:45 PM in reply to L V

    Hi,

     Free run should work, I don know what going wrong from your side. Please let us know, Have you probed the out pin of ADV7182A instead of final output from your board.

     And why the EVAL-ADV7182AEBZ command to read data immediately after command to write as below?

        We can read only by giving the read command, unless it will not read any registers.

     Please note that "Generally vertical scrolling implies the chip is not able to lock to Vsync.  Please make sure the input wave form is correct and the right amplitude".

     If low refresh rate,Please check with direct connection.If Jitter observed in direct, then turn off advanced features in the TV such as 3D comb etc. Refer here ADV7282A-M Vertical jitter - Q&A - Video - EngineerZone (analog.com)

    Thanks,

    Poornima

  • Hi all

    Sorry for my delay

    I found mistakes. The configuration for avd7182 is correct. I was wrong in sending data from fpga to the PC.

    Thanks you very much for your support.

    L V

  • 0
    •  Analog Employees 
    on Mar 26, 2021 10:16 AM in reply to L V

    Hi,

      Thanks for letting us know.

    Thanks,

    Poornima

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