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configuration for ADV7182A using FPGA via I2C

Hi all,

My project structure is VIDEO -> ADV7182A -> FPGA -> PC. I got EVAL-ADV7182AEBZ evaluation board and i used it to show video on montitor

Now i want to use only ADV7182A because i just need 8 pixel port and LLC clock.

I have configured ADV7182A  to use FPGA over the I2Cprotocol according to this

##02_CVBS SINGLE ENDED AUTODETECT ##

:Autodetect CVBS Single Ended In Ain 1, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7182
delay 10 ; Wait 10ms
42 0F 00 ; Exit Power Down Mode [ADV7182A writes begin]
42 52 CD ; SE_CVBS AFE IBIAS
42 00 00 ; CVBS in on AIN1
42 0E 80 ; ADI Required Write
42 9C 00 ; Reset Current Clamp Circuitry [step1]
42 9C FF ; Reset Current Clamp Circuitry [step2]
42 0E 00 ; Enter User Sub Map
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7182A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver [ADV7182A writes finished]
End

I have a problem that the image is not displayed as expected.(I got 27Mhz LLC clock and 28.63636 Mhz Crystal)

The picture below is not showing as expected. Rather, it doesn't show that many vertical black stripes.

Has anyone seen this problem??

Thanks!

Parents
  • Hi,

          Please try with different source and sink.  Some monitors will scale the incoming video to it's native resolution.  As an example suppose I have a monitor with native resolution of 1080p and the incoming stream is VGA60.  It will scale it up to 1080p to match the monitor.  This scaling can cause pixel by pixel distortion.
     Make sure the monitor is not in some sort of zoom mode and distorting the true image.     

        Also make sure with the chip power supplies are clean and well decoupled and make sure there is no noise getting injected into the ADC section of the chip.

    Thanks,

    Poornima

  • Hi PoornimaSubramani,

    Thanks for your help.

    I have followed your opinion. I have changed anotherPC, another monitor but nothing has changed. 

    I have checked power supply. Distance from ADV to FPGA is short and the layout is good enough to avoid noise.

    Do you have any idea?

    Thanks,

    L V

  • Hi,

    Could you please program the part into free-run mode. This will show if the issue is in the analog front end or digital back end.
    Please refer this FAQ https://ez.analog.com/video/w/documents/723/what-video-output-standard-does-the-adv7182-output-in-free-run-mode

    Also please crosscheck with direct(back to back) connection between CVBS source and Video monitor.

    Thanks,

    Poornima

  • Hi, sorry for my delay

    I checked free-run mode. It had same error and i used logic analyzer to check the transmitted message from PC to EVAL-ADV7182AEBZ evaluation board.

    I got many message and it is not like the script file. You can see in this video below.

    I wonder if I need to properly write the message readable in the video below onto the chip Or I just need to do exactly as described in the script file.

    Thanks!

  • Hi,

     Please let us know the configuration for free run mode?

     If free run means you should not give the input from the source, the ADV7182A will output the default color pattern when source is not connected.

     Also let us know, How you are running the I2C script?

    Thanks,

    Poornima

  • I followed this script for the free run mode and I got the same error.

    delay 10 ; Wait 10ms After Hardware Reset To Start I2C
    42 0F 80 ; Reset ADV7182
    delay 10 ; Wait 10ms
    42 0F 00 ; Exit Power Down Mode [ADV7182A writes begin]
    42 52 CD ; AFE IBIAS
    42 00 05 ; INSEL = unconnected input
    42 0C 37 ; Force Free run mode [Free run]
    42 14 11 ; Set Free-run pattern to 100% color bars [Free run]
    42 02 54 ; Force standard to NTSC-M [Free run]
    42 17 41 ; Enable SH1
    42 03 0C ; Enable Pixel & Sync output drivers
    42 04 07 ; Power-up INTRQ, HS & VS pads
    42 13 00 ; Enable ADV7182A for 28_63636MHz crystal
    42 1D 40 ; Enable LLC output driver [ADV7182A writes finished]
    End

    And i used the state machine in VHDL to run the script. Each command I put in a state machine. I checked I recorded the values in the registers as correct.

    So what can i do?

    I just need to use ADV7182 in mode CVBS SINGLE ENDED AUTODETECT Ain1??

    And why the EVAL-ADV7182AEBZ command to read data immidiately after command to write as below?

    drive.google.com/.../view

    Thanks!

    L V

Reply
  • I followed this script for the free run mode and I got the same error.

    delay 10 ; Wait 10ms After Hardware Reset To Start I2C
    42 0F 80 ; Reset ADV7182
    delay 10 ; Wait 10ms
    42 0F 00 ; Exit Power Down Mode [ADV7182A writes begin]
    42 52 CD ; AFE IBIAS
    42 00 05 ; INSEL = unconnected input
    42 0C 37 ; Force Free run mode [Free run]
    42 14 11 ; Set Free-run pattern to 100% color bars [Free run]
    42 02 54 ; Force standard to NTSC-M [Free run]
    42 17 41 ; Enable SH1
    42 03 0C ; Enable Pixel & Sync output drivers
    42 04 07 ; Power-up INTRQ, HS & VS pads
    42 13 00 ; Enable ADV7182A for 28_63636MHz crystal
    42 1D 40 ; Enable LLC output driver [ADV7182A writes finished]
    End

    And i used the state machine in VHDL to run the script. Each command I put in a state machine. I checked I recorded the values in the registers as correct.

    So what can i do?

    I just need to use ADV7182 in mode CVBS SINGLE ENDED AUTODETECT Ain1??

    And why the EVAL-ADV7182AEBZ command to read data immidiately after command to write as below?

    drive.google.com/.../view

    Thanks!

    L V

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