(ADV7182A) Can you tell us the detail about these register?

Hi 

Can you tell us the detail about these register?

Q1) IN_LOCK
Are the following conditions for locking in the case of NTSC?
   Horizontal sync signal (Hsync): Specified frequency ± 5% (Example: NTSC: 15.73kHz ± 5%)
   Vertical sync signal (Vsync): 40-70Hz
   Synchronized signal amplitude: 20% -200% (100% = 300mV @ PAL or 286mV @ NTSC)
   

Q2) LOST_LOCK
Do you recognize that LOST_LOCK will be performed when IN_LOCK is released?

Q3) FSC_LOCK
Are the following conditions for locking in the case of NTSC?
  Burst signal frequency: Specified frequency ± 1.3kHz (Example: NTSC: 3.5795MHz ± 1.3kHz)
  Burst signal amplitude: 5% -200% (100% = 300mV @ PAL or 286mV @ NTSC)

Q4) INST_HLOCK
Couldn't understood what this register doing.
Under what conditions do you lock?

Best regards

Kawa

Parents
  • Hi 

    Can somebody answer to my question?

    We need your information ASAP.

    Best regards

    Kawa

  • 0
    •  Analog Employees 
    on Jan 18, 2021 2:26 PM in reply to donadona999s

    Hi Kawa-San,

    Please find the below inline comments,

     Q1) IN_LOCK ?

        As per expert comment," The 100% specification for the decoder depends on the standard. It is therefore 286 mV for NTSC and 300 mV for PAL. The range was measured on the evaluation board, before the termination resistor and AC coupling cap for the ADV7181D, and before the resistor divider and AC coupling cap for the ADV7180/ADV7281/ADV7182 "
    By default the IN_LOCK bit work only shows if the ADV7180 has locked to the horizontal sync.

    The Hsync lock block in the ADV7180 has an internal counter that counts a number of good consecutive Hsync pulses. In standard mode the counter will count for approximately 1 second before setting the IN_LOCK bit high. In fast switch mode the counter will count for approximately 250 ms before setting the IN_LOCK bit high.

    A good Hsync has an amplitude that is between 20% and 200% of an expected value (e.g. 60 mV and 600 mV before voltage divider circuit). A good Hsync must also has a frequency that is +/- 5% of the expected value.

    Please refer the expert comment here https://ez.analog.com/video/f/q-a/5356/adv7180-details-of-the-condition-threshold-of-the-lost_lock-and-in_lock-bits/25968#25968

    Q2) LOST_LOCK
    Do you recognize that LOST_LOCK will be performed when IN_LOCK is released ?

       Alternatively the LOST_LOCK and  IN_LOCK bits can be used to determine if the ADV718x/ADV728x has locked, or lost lock, to a video source. Note in order for the LOST_LOCK and  IN_LOCK bits to work correctly the ADV718x/ADV728x must be programmed with an Analog Devices recommended script.

       Please refer here How to tell if the ADV7180/ADV7182/ADV728x has locked to a video source? - Documents - Video - EngineerZone (analog.com)

    Q3) FSC_LOCK

    As per the expert comment," The datasheet specifications state the minimum requirements that we need the CVBS signal to be in order for lock to occur. For example the color subcarrier in PAL needs to be 4.43 MHz +/- 1.3 kHz. If the CVBS signal has a color subcarrier outside this range than the ADV7180 will never lock to it. "

    Thanks,

    Poornima

  • Hi !

    Thank you for your reply.

    1. About IN_LOCK )
      If the horizontal sync signal has at least one line, the vertical sync signal has at least one field, and the conditions in the data sheet are met, the Status will be "1".
    2. About FSC_LOCK )
      Does FSC_LOCK also have a Status of "1" if at least one line meets the data sheet conditions?
    3. About IN_LOCK and FSC_LOCK )
      Under this judgment condition, I think that it can be detected only when there is no signal, is this correct?
      Also, other than IN_LOCK and FSC_LOCK, are there any Status Resisters that detect vertical synchronization deviations and are they aware of each other?
    4. About INST_HLICK)
      How about INST_HLOCK?
      Couldn't understood what this register doing.
      Under what conditions do you lock?

    Best regards

    Kawa

  • +1
    •  Analog Employees 
    on Jan 22, 2021 10:14 AM in reply to donadona999s

    Hi  Kawa-San,

    1) About IN_LOCK )
    If the horizontal sync signal has at least one line, the vertical sync signal has at least one field, and the conditions in the data sheet are met, the Status will be "1".     

     Basically, the timing for IN_LOCK and LOST_LOCK will depend on the settings of other controls, such as SRLS, FSCLE, CIL and COL. These status bits can be based on a line-to-line evaluation of the horizontal synchronization pulse of the incoming video, or on the evaluation of several fields (taking into account the vertical synchronization as well), as defined by SRLS.

    So i beleive, IN_LOCK bit high is not depending on the one line or one field from Hsync/Vsync.

     Note: Hsync lock block in the ADV7182A has an internal counter that counts a number of good consecutive Hsync pulses. In standard mode the counter will count for approximately 1 second before setting the IN_LOCK bit high. In fast switch mode the counter will count for approximately 250 ms before setting the IN_LOCK bit high.

    2. About FSC_LOCK
    Does FSC_LOCK also have a Status of "1" if at least one line meets the data sheet conditions?

      Generally FSC_LOCK bit only locks when ADV7182A has locked to the color bust. I don't think it will lock if it meet only one line.

    Please let us know, where the conditions are mentioned in the datasheet?

    3. About IN_LOCK and FSC_LOCK
    Under this judgment condition, I think that it can be detected only when there is no signal, is this correct?
    Also, other than IN_LOCK and FSC_LOCK, are there any Status Resisters that detect vertical synchronization deviations and are they aware of each other?

      By reading 0x49(Raw status 3) register ,We could able to know whether Vsync/Hsync lock has established or not.

    Note: IN_LOCK shows if the ADV7182A has locked to the horizontal sync. FSC_LOCK shows if the ADV7180 has locked to the color subcarrier frequency.

    4.About INST_HLICK)
    How about INST_HLOCK?
    Couldn't understood what this register doing.
    Under what conditions do you lock?

      INST_HLOCK is an instantaneous horizontal lock indicator, so it must be based on a line-to-line evaluation of the horizontal synchronization pulse of the incoming video, and is very likely to be faster than the IN_LOCK and LOST_LOCK status bits.

    Please note that IN_LOCK is a far more reliable indication that horizontal lock has been achieved than INST_HLOCK.

    Thanks,

    Poornima

  • Hi 

    Thank you for your answer.

    I understood.

    Best regards

    Kawa

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