How to configure ADV7612 if you want to receive video at multiple resolutions?

How to configure ADV7612 if you want to receive video at multiple resolutions?

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  • 0
    •  Analog Employees 
    on Jan 5, 2021 11:23 AM 1 month ago

    Hi,

     We can't configure ADV7612 for multiple resolutions simultaneously by using more than one ADV7612 i.e Only one ADV7612 can access the AV buses at a time, the second must remain tri-stated.

     Here you can find the more information about the usage of two ADV7612  https://www.analog.com/media/en/reference-design-documentation/reference-designs/CN0224.pdf

     But ADV7612 is a dual port XpressviewTm 225 MHz HDMI® receiver that allows fast switching between two inputs.

    Thanks,

    Poornima

  • Configure adv7612 through FPGA driver, when the video input resolution changes, do the registers of adv7612 need to be reconfigured?

  • Thank you very much for your help, I know how to configure ADV7401/ADV7403 to receive non-standard video. But I am still unclear about the register configuration of adv7612 to receive non-standard video.

    1) Please refer to the register LATCH_CLK[3:0], PLL_DIV_MAN_EN, PLL_DIV_RATIO[11:0] in the reference document, which registers correspond to adv7612?

    2)In the case of free running mode 1, can it be possible to receive non-standard videos (for example, the resolution is 1440X900@60hz) by programming the registers CH1_FR_LL, CP_LCOUNT_MAX and INTERLACED?

  • Thank you very much for your help, I know how to configure ADV7401/ADV7403 to receive non-standard video. But I am still unclear about the register configuration of adv7612 to receive non-standard video.

    1) Please refer to the register LATCH_CLK[3:0], PLL_DIV_MAN_EN, PLL_DIV_RATIO[11:0] in the reference document, which registers correspond to adv7612?

    2)In the case of free running mode 1, can it be possible to receive non-standard videos (for example, the resolution is 1440X900@60hz) by programming the registers CH1_FR_LL, CP_LCOUNT_MAX and INTERLACED?

  • +1
    •  Analog Employees 
    on Jan 18, 2021 1:28 PM 1 month ago in reply to KSfafa@126.com

    Hi,

    1) Please refer to the register LATCH_CLK[3:0], PLL_DIV_MAN_EN, PLL_DIV_RATIO[11:0] in the reference document, which registers correspond to adv7612?

       Please let us know, you have the source that can generate 1440X900@60hz?

    2)In the case of free running mode 1, can it be possible to receive non-standard videos (for example, the resolution is 1440X900@60hz) by programming the registers CH1_FR_LL, CP_LCOUNT_MAX and INTERLACED?

     As per specification "It is also possible to custom program the resolution that the ADV7611 should expect for free run Mode 1 by programming the free-run line length, line count max, and interlaced registers. Please refer to the Free Run Mode section for the configuration of these registers".

    Thanks,

    Poornima

  •   1)When the two resolutions of CH1_FCL, CH1_BL, CH1_LCF, CH1_LCVS are very similar, how to distinguish between the two different resolutions (for example, 640*400@85HZ and 720*400@85HZ)?

    2)Can the measured value of the STDI register and the TOTAL_LINE_WIDTH register of the HDMI MAP part be used to distinguish the input resolution?Are the measured values of these two registers valid at the same time?If they are not both effective, then who is effective first?

    3)If the measurement value of the STDI register and the TOTAL_LINE_WIDTH register of the HDMI MAP part can be used to distinguish the input resolution, should the measurement valid indicator use CH1_STDI_DVALID or DE_REGEN_FILTER_LOCKED? Or do they use their own?

  • 0
    •  Analog Employees 
    on Jan 25, 2021 12:23 PM 1 month ago in reply to KSfafa@126.com

    Hi,

      Please find the below inline comments,

    1) When the two resolutions of CH1_FCL, CH1_BL, CH1_LCF, CH1_LCVS are very similar, how to distinguish between the two different resolutions (for example, 640*400@85HZ and 720*400@85HZ) ?

       - By using STDI block(signal detection and identification) we can distinguish these two standard.

    2)Can the measured value of the STDI register and the TOTAL_LINE_WIDTH register of the HDMI MAP part be used to distinguish the input resolution?Are the measured values of these two registers valid at the same time?If they are not both effective, then who is effective first?

        - STDI - Standard Detection and Identification. It measures active synchs so you can determine what video format is coming in
       STDI block measures the format parameters by using registers CHx_BL, CH2_LCVS, CHx_LCF, CHx_FCL.
       Below are the four key measurements, that STDI blocks can perform,
      • Block
            Length CHx_BL[13:0] This is the number of 28.6363 MHz clock cycles (XTAL frequency) in a block of eight lines.
    From this, the time duration of one line can be concluded.
    • Line Count in Field CHx_LCF[10:0] The CHx_LCF[10:0] readback value is the number of lines between two VSyncs,that is, over one field measured by channel x.
    • Line
         Count in VSYNC CHx_LCVS[4:0] The LCVS[4:0] readback value is the number of lines within one VSync period.
    • Field
         Length CHx_FCL[12:0] This is the number of 28.6363 MHz clock cycles in a 1/256th of a field.
    Alternately, this value of FCL multiplied by 256 gives one field length count in 28.6363 MHz (XTAL) clocks.
    Read the parameters and calculate the format,assume CHA_BL = 6039 -> time of one line = 6039 / 28,636,363 / 8 = 26.36us which would point to SVGA60, 800x600@60.
    Please refer here https://ez.analog.com/video/f/q-a/11767/stdi-block-in-the-adv7611-device/36440#36440

    3)If the measurement value of the STDI register and the TOTAL_LINE_WIDTH register of the HDMI MAP part can be used to distinguish the input resolution, should the measurement valid indicator use CH1_STDI_DVALID or DE_REGEN_FILTER_LOCKED? Or do they use their own ?

        Please make sure TMDSPLL_LCK_A_RAW and V_LOCKED_RAW are high. This implies the chip is locked to the incoming format
        Then second check CH1_STDI_DVALID to see if the STDI module has valid data.
        Third read various values STDI to determine the input format" .

    Thanks,

    Poornima

Reply
  • 0
    •  Analog Employees 
    on Jan 25, 2021 12:23 PM 1 month ago in reply to KSfafa@126.com

    Hi,

      Please find the below inline comments,

    1) When the two resolutions of CH1_FCL, CH1_BL, CH1_LCF, CH1_LCVS are very similar, how to distinguish between the two different resolutions (for example, 640*400@85HZ and 720*400@85HZ) ?

       - By using STDI block(signal detection and identification) we can distinguish these two standard.

    2)Can the measured value of the STDI register and the TOTAL_LINE_WIDTH register of the HDMI MAP part be used to distinguish the input resolution?Are the measured values of these two registers valid at the same time?If they are not both effective, then who is effective first?

        - STDI - Standard Detection and Identification. It measures active synchs so you can determine what video format is coming in
       STDI block measures the format parameters by using registers CHx_BL, CH2_LCVS, CHx_LCF, CHx_FCL.
       Below are the four key measurements, that STDI blocks can perform,
      • Block
            Length CHx_BL[13:0] This is the number of 28.6363 MHz clock cycles (XTAL frequency) in a block of eight lines.
    From this, the time duration of one line can be concluded.
    • Line Count in Field CHx_LCF[10:0] The CHx_LCF[10:0] readback value is the number of lines between two VSyncs,that is, over one field measured by channel x.
    • Line
         Count in VSYNC CHx_LCVS[4:0] The LCVS[4:0] readback value is the number of lines within one VSync period.
    • Field
         Length CHx_FCL[12:0] This is the number of 28.6363 MHz clock cycles in a 1/256th of a field.
    Alternately, this value of FCL multiplied by 256 gives one field length count in 28.6363 MHz (XTAL) clocks.
    Read the parameters and calculate the format,assume CHA_BL = 6039 -> time of one line = 6039 / 28,636,363 / 8 = 26.36us which would point to SVGA60, 800x600@60.
    Please refer here https://ez.analog.com/video/f/q-a/11767/stdi-block-in-the-adv7611-device/36440#36440

    3)If the measurement value of the STDI register and the TOTAL_LINE_WIDTH register of the HDMI MAP part can be used to distinguish the input resolution, should the measurement valid indicator use CH1_STDI_DVALID or DE_REGEN_FILTER_LOCKED? Or do they use their own ?

        Please make sure TMDSPLL_LCK_A_RAW and V_LOCKED_RAW are high. This implies the chip is locked to the incoming format
        Then second check CH1_STDI_DVALID to see if the STDI module has valid data.
        Third read various values STDI to determine the input format" .

    Thanks,

    Poornima

Children
  • Thank you for your reply, but this is not the answer I want, I know how to use STDI.

    1)What I want to know is what to do when the two resolutions cannot be distinguished by the STDI register measurement value. For example, for the two resolutions of 640*400@85HZ and 720*400@85HZ, the respective values of their STDI registers are very close, as shown in the figure. How to distinguish at this time?

    2)Can the readback value of STDI register and the readback value of ‘HDMI SYNCHRONIZATION PARAMETERS’ be used at the same time to estimate the video resolution of the incoming HDMI stream?

    The reference document on'HDMI SYNCHRONIZATION PARAMETERS' gives the description as shown in the figure below.

    Thanks

  • 0
    •  Analog Employees 
    on Jan 27, 2021 9:32 AM 1 month ago in reply to KSfafa@126.com

    Hi,

     By using pixel clock you can distinguish the above two formats,

     Also It seems marked timing parameters only remain same, the remaining timing parameters like Hor/Ver blank start blank time total time are almost different only.

    2)Can the readback value of STDI register and the readback value of ‘HDMI SYNCHRONIZATION PARAMETERS’ be used at the same time to estimate the video resolution of the incoming HDMI stream?

        Yes, You can.

    Thanks,

    Poornima

  • Thank you very much for your reply.

    I have one more question to ask.

    Most of the parameter values of the two resolutions of 1360*768@60HZ and 1366*768*60HZ are very similar (as shown in the figure below), I can distinguish the two resolutions only by the difference in the readback value of the STDI register CH1_LCVS ? Is this reasonable? (CH1_LCVS of 1360*768@60HZ is 6 lines, and 1366*768*60HZ is 3 lines)

    Thanks again for your help.

  • 0
    •  Analog Employees 
    on Jan 28, 2021 11:22 AM 1 month ago in reply to KSfafa@126.com

    Hi,

     Most of the parameter values of the two resolutions of 1360*768@60HZ and 1366*768*60HZ are very similar (as shown in the figure below), I can distinguish the two resolutions only by the difference in the readback value of the STDI register CH1_LCVS ? 

       Yes, I believe you can use CH1_CL, CH1_LCF CH1_LCVS and FCL readback to distinguish the resolution.

    Thanks,

    Poornima