(ADV7482)Flicker when blue image is input to CVBS

Hi

When my customer enter 100% blue from CVBS, the whole or part of the screen seems to flicker.

If it is all blue, it will be noticeable, if it is green, it will be visible or invisible depending on the person, and if it is red, flicker will not be visible.
The lower the brightness level, the more noticeable the impression.
* Video signal is input from the signal generator

Such a symptom does not occur when BT.656 is inserted via a decoder of another company.
The documentation says that the VREFP-VREFN capacitors should be mounted on the same side, so the wiring is routed and placed a little further away.

Is the position of the VREFP-VREFN capacitor a factor that causes flicker?
Also, although it is written on the circuit diagram that it should be mounted on the same surface as the device, the layout of the evaluation board is mounted on the opposite side of the device at the shortest distance.


Is it better to mount it on the same side or on the back side?
I want an answer right away.

Best regards

Kawa



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[edited by: donadona999s at 5:46 AM (GMT -5) on 10 Dec 2020]
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  • 0
    •  Analog Employees 
    on Dec 10, 2020 1:46 PM 4 months ago

    The goal is to keep this cap as close to the pins as possible, preferably on the same side but it will work on the opposite side also.

    Check the amplitude of the signal at the input pin.  Make sure the color burst is correct.  

  • Hi GuenterL

    Thank you for your support.

    Can you help about this?

    (1) What are the uses of VREFP and VREFN?

    (2) Please disclose the internal circuits of VREFP and VREFN as much as possible.  

          It can be a block diagram.

    (3) Both ADV7182 and ADV7482 have VREFP and VREFN terminals.

          But please explain the difference in circuit configuration in the circuit diagram of the evaluation board.
    (4) The hardware manual of ADV7482 states that they should be placed on the same side.

          But on the evaluation board, they are placed directly behind the IC. Which is correct?
    (5) The hardware manual of ADV7482 does not indicate the recommended circuit for the VREFP and VREFN terminals.

           Please re-post the explanation and precautions on how to use it.
    (6) It is presumed that the capacitor is placed between VREFP and VREFN assuming a differential input, but isn't it necessary to place it only for single-ended input? 

         On the contrary, when using it with a single end, isn't it necessary to have a capacitor between GND?

    Noise with a period of about 16us has been confirmed in VREFP and VREFN at 50mVp-p.

    Also, when the decaps of P and N are removed, a relatively large (several hundred mV) ripple of about 6.4 MHz is observed, and although I forgot either P or N, the frequency changes to 4.5 MHz when probing. It has been observed.

    I can't say anything because it's in an irregular state, but since it matches the frequency when the vertical stripes are frequency-analyzed, I feel that there is some sensitivity in how to attach the capacitor between P and N.

    Best regards

    Kawa

  • +1
    •  Analog Employees 
    on Jan 12, 2021 2:45 PM 2 months ago in reply to donadona999s

    1) Both ADV7182 and ADV7482 use similar ADCs which requires clean and stable reference voltages.  The Vrefp and Vrefn pins provides a connection to the internal reference generators to decouple noise beyond that which the silicon can do.

    2) I have no further internal circuit references beyond that which is exposed in the data sheets.

    3) Both schematics I looked at have the same VREF circuit, just a 0.1uF cap between the 2 pins

    4) Ideally the VREF cap should be placed on the same side of the PCB as the chip.  However is can be placed on the opposite side of the PCB if it cannot be placed on the same side.  The goal is to keep the traces as short and clean as possible.

    5) VREFP and VREFN should only have a 0.1uF ceramic cap places as close as possible to the pins.  Any noise injected into those 2 pins will affect the ADCs

    6) The decoupling cap should be placed regardless if the source is single or differential inputs.

    This decoupling cap helps clean up the reference voltages.  I am not surprised you would see 6.4MHz, I just don't know it's source.  When scope probing it is possible you are injecting noise into the reference generators.  Remember the probe tip has capacitance and connection back to the scope itself.

    Ideally if the cap is as close to the pins as possible all should be good.  Make sure you are not injecting any noise from other traces into the vref taces.

Reply
  • +1
    •  Analog Employees 
    on Jan 12, 2021 2:45 PM 2 months ago in reply to donadona999s

    1) Both ADV7182 and ADV7482 use similar ADCs which requires clean and stable reference voltages.  The Vrefp and Vrefn pins provides a connection to the internal reference generators to decouple noise beyond that which the silicon can do.

    2) I have no further internal circuit references beyond that which is exposed in the data sheets.

    3) Both schematics I looked at have the same VREF circuit, just a 0.1uF cap between the 2 pins

    4) Ideally the VREF cap should be placed on the same side of the PCB as the chip.  However is can be placed on the opposite side of the PCB if it cannot be placed on the same side.  The goal is to keep the traces as short and clean as possible.

    5) VREFP and VREFN should only have a 0.1uF ceramic cap places as close as possible to the pins.  Any noise injected into those 2 pins will affect the ADCs

    6) The decoupling cap should be placed regardless if the source is single or differential inputs.

    This decoupling cap helps clean up the reference voltages.  I am not surprised you would see 6.4MHz, I just don't know it's source.  When scope probing it is possible you are injecting noise into the reference generators.  Remember the probe tip has capacitance and connection back to the scope itself.

    Ideally if the cap is as close to the pins as possible all should be good.  Make sure you are not injecting any noise from other traces into the vref taces.

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