[AD7391] Color artifacts

Hi Poornima,

Thankyou for your answer.

PoornimaSubramani said:

For color burst, 27MHz is spec'd as +-2ns for the ADV7393 clock input with a minimum 40-60% duty cycle.

  Generally FPGA clock outputs are not very stable or accurate.  This may cause color distortion and this is why you will see all our reference designs using crystals or oscillators for the 27MHz source. 

For sure my clock is not as clean as if it were generated by a xtal.

Nevertheless I cannot explain why the same "dirty" clock, after each reset, sometimes work well and sometimes not.

I clarify: after every reset the Encoder is able to generate a good or not good (the result is apparently randomly distributed) signal keeping this state until the next reset.

If the Problem is the clock, then I would expect always the same result.

Then I cannot explain why if I use the same "still" image (captured Frame) and using the same clock I never see the Problem.

If the Problem were the clock, I would expect the same behaviour also in the "still" Image.

It appears to me that something is interferring in some initialization procedure inside the Encoder.

Could you provide more info about the internal procedure to help me in understand the Problem?

PoornimaSubramani said:

Please refer Table 96 and Table 97 - 8-Bit PAL Square Pixel/16-Bit PAL Square Pixel in datasheet, some configuration are different from your side and crosscheck your configuration according to the Tables.

I also try to use exactly the same configuration advised in the datasheet (8-bit PAL square pix) but I get the same results.

PoornimaSubramani said:

Also Please note that for flicker please make sure your power supplies are clean and very stable.Video flicker, may occur due to noise, either on the power supplies or on something else.Also try disabling the PLL (Register 0x00[1]) and see if this reduces flicker. If it does, your PVDD supply has noise on it.

About the Video flicker it is not a Problem, I can only see some cross luminance effect on the Color Transition edge, the rest is acceptable.

I'm looking Forward to hering from you.

Hi,

 If FPGA as generating the sync, there might be a chance of color display problem in some custom boards, i.e When operating the encoder as a slave (HSync and VSync generated by FPGA) the problem may remains, so try to doing the same using EAV/SAV coding, there might be chance of colors may displayed correct.

 Also any impedance mis-match can also cause ghosting or reflections.  Expert suggested a simple tool here that can give you a first pass estimate of what the trace impedance is for various board stack ups and trace widths. Please crosscheck with your board with impedence calculator

PCB Trace Impedance Calculator 

Thanks,

Poornima

Hallo,

I just tested using the following configuration:

{0x17,0x02},
{0x00,0x1C},
{0x01,0x00},
{0x80,0x11},
{0x82,0xD3},
{0x84,0x00},
{0x87,0x00},
{0x89,0x03},
{0x8C,0x0C},
{0x8D,0x8C},
{0x8E,0x79},
{0x8F,0x26},
{0xA2,0x07}

But the results is the same.

Regards.

Hi,

  Please enable the below configuration as it is and let us know and also make sure whether you are giving 16 bit RGB input from the source.

16-Bit PAL Square Pixel RGB In, CVBS/Y-C Out.

Subaddress       Setting       Description  
 
0x17             0x02          Software reset.

0x00             0x1C          All DACs enabled. PLL enabled (16×).

0x01             0x00          SD input mode.

0x80             0x11          PAL standard. 
                               SSAF luma filter enabled. 
                               1.3 MHz chroma filter enabled.

0x82             0xD3          Pixel data valid. 
                               CVBS/Y-C (S-Video) out. 
                               SSAF PrPb filter enabled. 
                               Active video edge control enabled. 
                               Square pixel mode enabled.

0x87            0x80           RGB input enabled.

0x88            0x10           16-bit RGB input enabled.

0x8A            0x0C           Timing Mode 2 (slave). HSYNC/VSYNC synchronization.


0x8C            0x0C    
0x8D            0x8C           Subcarrier frequency register values for CVBS and/or S-Video (Y-C) output in PAL square pixel mode (29.5 MHz input clock).
0x8E            0x79    
0x8F            0x26


Thanks,
Poornima

Unfortunatelly the bord where I'm experimenting the problem have only the 8-bit interface.

Best Regards.

Hi,

  Please change the 0x88 register value as 0x18(0x88 0x18) and keep the remaining configuration as it is for 8 bit interface.

Thanks,

Poornima

Hallo,

using this configuration:

{0x17,0x02},
{0x00,0x1C},
{0x88,0x18},
{0x80,0x11},
{0x82,0xD3},
{0x84,0x00},
{0x87,0x00},
{0x89,0x03},
{0x8C,0x0C},
{0x8D,0x8C},
{0x8E,0x79},
{0x8F,0x26},
{0xA2,0x07}

and keeping the data input with 8-bit Y/CbCr I get a compleatly flase color image.

Regards.

Hi,

 If you are using the data input as 8-bit YCbCr, then you need to configure the 0x88 register value as 00.

 Also if you are using 0xA2 register, in that case you need to enable 0x87 bit 4 as '1' - i.e SD luma SSAF gain/attenuation(only applicable if Subaddress 0x87, Bit 4 = 1).

Thanks,

Poornima

So it seems that you advice me to configure the encoder like I described in the first post.

I'm wrong?

Regards.

Hi,

 But in first post it seems, you haven't configure the 0x88 register for YCbCr input right?

Thanks,

Poornima

Yes, because the 0x88 default valus is 0x00: 8-bit YCbCr input.

Hi,

 Don't know, where the artifacts arises,Could you please check the reference schematic

 Also make sure with loop filter, If they are changed you may not lock onto the incoming video or periodic drop outs of the output.

Thanks,

Poornima

Hi,

 Don't know, where the artifacts arises,Could you please check the reference schematic

 Also make sure with loop filter, If they are changed you may not lock onto the incoming video or periodic drop outs of the output.

Thanks,

Poornima