[ADV739x]About the Specifications

Hi

I have some questions about the ADV739x.

Could you please confirm my questions?

1) About the power startup and shutdown.
Are there any order or restrictions on power up and down?

2) About the reset release sequence
I would like to know the relationship between start of the clock input and time of the release the reset.

3) The resistor connected to the DAC is 4.12kohm, is it okay to use more than one resistor?
(For example, 3.9kOhm + 220Ohm)

4) Is there a limit to the time from Stop Condition to Start Condition of I2C communication?

5) About digital video input settings
I assume 16-bit mode of ED/HD SDR.
I understand that I enter the least significant bit of CbCr into P0, And I understand that the lowest bit of Y is input to P8.
Is my understanding correct?

Best regards,

mountain999

  • I wrote ADV739x, but the products I want to know are ADV7392 and ADV7393.

  • 0
    •  Analog Employees 
    on Oct 28, 2020 11:14 AM 27 days ago in reply to mountain999

    Hi,

    1) Are there any order or restrictions on power up and down?

      As per expert comment  "Normally our reference boards bring 3.3 and 1.8V rails up and down at the same time.  As long as 1.8 does not exceed 3.3V for extended period of time you should be OK.  You can always put a schottkey diode between 1.8 to 3.3V in case 3.3V drops much faster then 1.8V does".

    2) About the reset release sequence

        Normally we give 5ms after reset goes high.

        After setting the Chip RESET bit (or initiating a reset via the pin), the part returns to the default mode of operation with respect to its primary mode of operation, and so on. All I2C bits will be loaded with their default value, which makes this bit self-clearing.

    • Executing a software reset takes approximately 2 ms. However, it is recommended to wait  5ms before any further I2C writes are performed.

    • The I2C master controller will receive a no acknowledge condition on the ninth clock cycle  when Chip Reset is implemented.

    • It is recommended to wait 5 ms after the low pulse before an I2C write is performed.

    Note:   Setting the Chip RESET bit is equivalent to controlling the Reset pin on the ADV739x and will issue a full chip reset. All I2C registers will be reset to their default values. After the reset sequence, the part will immediately start to acquire the incoming video signal.

    3) The resistor connected to the DAC is 4.12kohm, is it okay to use more than one resistor?
    (For example, 3.9kOhm + 220Ohm).

      I beleive you can.

    For full-drive operation (for example, into a 37.5 Ω load), a 510 Ω resistor must be connected from RSET to AGND.
    For low-drive operation (for example, into a 300 Ω load), a 4.12 kΩ resistor must be connected from RSET to AGND.

    Note:  External filter and buffer components connected to the DAC outputs should be placed as close as possible to the ADV7390/ ADV7391/ADV7392/ADV7393 to minimize the possibility of noise pickup from neighboring circuitry and to minimize the effect of trace capacitance on output bandwidth. This is particularly important when operating in low-drive mode (RSET = 4.12 kΩ, RL = 300 Ω).

    4) Is there a limit to the time from Stop Condition to Start Condition of I2C communication?

            For i2c write sequence,it takes 8 cycle between  start bit and  stop bit.
            Bus free time between a STOP and START conditions for different mode as follows,
                For standard mode-- min time-4.7 us
                For Fast Mode    -- min time-1.3 us
    Also Please refer i2c bus specification.

    Refer https://ez.analog.com/video/f/q-a/5291/adv7180-i2c-timing-parameters

    Note: Start condition - write operation (sub address) - Start condition - Read operation (data) - Stop condition
        Need to send STOP bit  when the whole process reading is done.To terminate a read/write sequence a stop signal must be sent. 

    5) About digital video input settings
    I assume 16-bit mode of ED/HD SDR.
    I understand that I enter the least significant bit of CbCr into P0, And I understand that the lowest bit of Y is input to P8.
    Is my understanding correct?

        Yes, You are right.

    Thanks,

    Poornima

  • Hi,

    Very thanks for your answer.

    I have additional question about 2).

    So, Could you please confirm below?

    2-1)

    Are there any restrictions on the relationship between CLKIN and RESET?

    (For example, CLKIN needs to be supplied faster than RESET.)

    Best regard

    mountain999

  • 0
    •  Analog Employees 
    on Oct 29, 2020 10:21 AM 26 days ago in reply to mountain999

    Hi,

      As per expert comment "CLKIN is not required for RESET". RESET returns the device back to it's power up state.
      Actually clock input is required only for 5ms before applying reset.
      Also Please refer here ADV7390 CLKIN Frequency

    Thanks,

    Poornima