ADV7842 LLC Phase Adjustment Test

We have a galvanic isolated connection between ADV7842 and TFP410 using a 24-bit pixel bus, as depicted below.

We plan to implement an LLC phase calibration during production based on the pass/fail shmoo-plot approach.

I tried setting 8 different phase values for the LLC (over the entire range) and also the two CLK input polarities of TFP410 (rise / falling) during a 1080p60 (Full HD) video capture.

I could see the phase changes in the oscilloscope comparing the LLC and one of the 24-bit signals, but nothing happened with the video being captured.

Shouldn’t I see any disturbances?


  • 0
    •  Analog Employees 
    on Oct 6, 2020 5:02 PM 1 month ago


     Please refer the below expert comment

    " Normally a board will have 6-8 phase step range that works correctly.
     From this you can pick a step in the middle of that range.
    Using this pick then for 162MHz you will have +-192 fs to the previous or next step,  
    So for initial timing analysis I would pick a data transition point midway through a clock cycle and set its valid data time to +-192 fs.
    If analysis of the FPGA timing has issues I keep in mind I can move the data transition point to anywhere within the 32 step range.
    Bottom line is the data transition point can be set to any of the 32 step values and some of there points will meet FPGA timing requirements 162MHz was selected for that thread since it's the fastest pixel rate the device will see.
    There is no hard data on step accuracy versus voltage/temperature/process variations.
    It really does not matter since in general good steps should b 6-8 steps width which if the middle step is picked.
    It will handle any voltage/temperature/process variations."
    Please refer



  • Hi Poornima.

    The thread you referred to is from our project. You can see my discussions with Guenter at the end.
    My point here is that all 32 phase steps seem to be good for me. As I mentioned, I tried 8 different phase settings over the entire range and also flipping the polarity of TFP410 input clock and nothing happened with the captured image.

    It worked no matter what phase and polarity combinations I tried. I confirmed that the phase really changed using an oscilloscope.

    Shouldn't I see disturbances in some settings?


  • 0
    •  Analog Employees 
    on Oct 6, 2020 6:43 PM 1 month ago in reply to Eduardo

    With 1080p I'd expect to see at least one data/clock phase setting that would cause problems.  If the TFP410 input has some very small setup and hold times, it might not matter.  

    Make sure you are seeing the phase adjustments on the LVDS->LVTTL output.

  • Hi Guenter.

    I probed directly at the input of TFP410.

    Tsu = 1.2ns (min.) and Th = 1.3ns (min.).

    Tracks are perfectly length matched so we just have the propagation delays of the components we discussed before.

    If they all fit in the typical values, there's a very good chance bits are closely aligned and this may explain why I don't see disturbances. Do you agree?

    What kind of disturbances should I see? An image glitch, video noise or sync loss?

    I thought about trying to replace one of the many isolators in the pixel bus by wiring connections, in a way to force a delay change in the bus and see that happens.


  • 0
    •  Analog Employees 
    on Oct 6, 2020 8:08 PM 1 month ago in reply to Eduardo

    I am surprised you don't see any video problems at one of steps.  Not a problem, just surprised.

    Given that the TFP410 latches the incoming data on the rising edge of clock, measuring at the TFP410 inputs, I would adjust the ADV7842 phase until the the clock rising edge is in the middle of any data transitions.

    Regarding what kind of disturbance I'd expect:

    1) loss of V or H sync.  lock issue to the sync pulse, causing by pixel clock jitter of the sync pulses

    2) pixel twinkling or noise.

    If you select the wrong phase step (where clock and data transitions overlap) the problems may show up over temperature or voltage drift. 

    Bottom line is to adjust the clock edge to the middle of the data transition measured at the TFP410 input pins and you should be safe.