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Interlaced feed on ADV7281-M

Team,  

  We are currently facing a concern, the below s our configuration( please ignore the LVDS path)

We are getting an interlaced feed to the infotainment , which uses a ADV7281 decoder, when we read the status register 0x13 on 7281m we get a value of 0x69 confirming interlaced feed , also the register 0x45 on reading always returns 0xB6 which confirm even field , How do we ensure that the odd frames are received ? we want to try the deinterlacing on the SOC, but we are not sure if both the odd and even fields are making it to CSI peripheral, is there a setting or a way to ensure this? 

  • Hi,

      Generally in interlaced display is made using two fields, each one containing one-half of the scan lines needed to make up one frame of video. Each field is displayed in its entirety—therefore, the odd field is displayed, then the even, then the odd,and so on. Fields only exist for interlaced scanning systems. So please refer field change related register in Page91 at ADV728x Hardware Manual

      Also set the CSI_FRAME_NUM_CTL(0x1F) in CSI map, if it is an interlaced video.

    Thanks,

    Poornima

  • Poornima,

     We read the registers , 0x46 register and found that  SD_FIELD_CHNGD_Q is 1, which indicates that the field is changing , but reading  EVEN_FIELD on register 0x45 returns true all the time (0xB6), we are never able to find that field being set to odd field.

    Also the Pins i think are available only in ADV7280 and we are using the ADV7281 model, Can you help on what is probably going wrong?

  • Hi,

     Is it possible for you to verify the below things,

      Please note that in interlaced mode odd frames have one extra line than even frames,

    In Interlaced mode :
     The even odd field information is included in embedded in the digital synchronization signals.
     It is also possible to use the VS/FIELD/SFL pin to determine even/odd fields.
     In this mode the VS/FIELD/SFL pin is programmed to output field synchronization pulses.
    In Progressive mode:
        The field bit goes low and stays low in progressive mode. i.e. even/odd information is not sent in embedded digital synchronization signals.
        The field synchronization pin will go low and stay low in progressive mode. i.e. even/odd information is not over synchronization pins.

    Thanks,

    Poornima

  • Poornima,

     As i had indicated the ADV7281 doesn't have the SFL,HSYNC and VSYNC  and instead has 3 GPIO Pins.

    So is there any other option or is it possible to configure the GPIO to output the field information 

  • Hi,

     In GPIO pin, you can able to configure Input/Output only.

     By using clock rate, you can know right whether interlaced or progressive format is displaying.

     I2P works by 'line-doubling' i.e. outputting the same line twice and doubling the MIPI CSI-2 clock speed. Please note that In interlaced mode the ADV7282-M outputs with a 216 Mbps data rate (MIPI clock frequency 108 MHz).
    In progressive mode (i.e. I2P mode on) the ADV7282-M outputs a 432 Mbps data rate ( MIPI clock frequency 216 MHz).

    Note: By default, the MIPI CSI-2 frame start/end packets and the MIPI line start/end packets are output by the ADV7280-M, ADV7281-M, ADV7281-MA, or ADV7282-M transmitter device.These fields are separated by EAV/SAV codes and vertical blanking periods.
      SAV contains an F bit which tells specifies even/odd field,The F bit will change between 0 and 1 to indicate if the field is an odd or even field.

    Thanks,

    Poornima

  • Poornima,

    we are continuously probing the register 0x45 to see if there is any change in the field, it always returns EVEN_FIELD , even though the input is interlaced.

    What is the possibility for this?

    We are observing a half display on the target with second half being a grey patch. 

    We are basically trying to de-interlace on SOC and are observing that Odd field(F=1) is missing.

  • Hi,

     Please let me know, Are you facing the issue only with particular interlace format or all?

     finally you are displaying the de-interlaced output right (i.e Progressive Out), Just try with interlaced output without doing the de-interlacing on SOC.

     Also please crosscheck your schematics with reference one 1803.ADV7280_MSchematic.zip

    Thanks,

    Poornima