I use I2c to configure ADV7393 with fpga(kintex7) on my custom hw. But, it has no return ack to the command that i write thro i2c protocol that complies with the datasheet. I have tried SCL frequency for 400 kHz, 200 kHz, 50 kHz. But, nothing is changed. It also comply with SDA delaying that changes after falling edge of SCL. (I tried otherwise).
I have a ADV7192A/ADV7391 evoluation board. As you can see on the datasheet, ADV7391 and ADV7393 are mostly similar encoders (not different powerups, register sets, ..). I jumpered SCL and SDA test points to my custom board and tried to configure ADV7393 whose ALSB port tied to ground (0x54). And, it failed. I tried to configure encoder and decoder chips on evaluation board from my custom board to be free running NTSC. It worked.
I checked clock that is 27Mhz, power rails (1.8V, 3.3V), reset pin and it seems nothing is wrong.
I also checked some of the issues and solutions on the community which are posted below.
There are some exceptions to allow the user to continue to communicate with the part via I2C: the RESET, ALSB, SDA and SCL pins are kept alive.ALSB should be pulled high or pulled low. At power up…
Please try to check your RTL I2C controller, Try not to use Xilinx I2C controller.
thank you for the reply. It's my own i2c controller hdl design that meets the i2c specification. I have tested it on many devices. Also, It has programmed adv7182A/7391 on evalboard.
I wonder that this problem may be related harware reset sequence. Resetn signals stays low and high enough as described on the document before initiated any i2c command (60 ms low and 60 ms high). And, i have tried not to provide clock during this period. I have 2 different board and 6 different adv7393 and tried them all. But, the result is same.
i think so. Sda data line changes at the half of the scl low period. If my calculation is correct, it would be 1.25 us at 200kHz and 5 usn at 50kHz. I have also tried 1Khz.
can u provide oscilloscope snapshot of SDA vs SCL for atleast 10 CLK cycles
The device address is 0x54 and it runs at 1kHz.
i have also tried an address scan from 0x00 to 0x7F. It has no return ack.
There are some exceptions to allow the user to continue to communicate with the part via I2C: the RESET, ALSB, SDA and SCL pins are kept alive.ALSB should be pulled high or pulled low. At power up the pin is checked to see which I2C slave address it will respond to.THE I2C DEVICE ADDRESS IS CONFIGURABLE USING THE ALSB PIN: 1. ALSB = 0, I2C DEVICE ADDRESS = 0xD4 (ADV7390/ADV7392) OR 0x54 (ADV7391/ADV7393) 2. ALSB = 1, I2C DEVICE ADDRESS = 0xD6 (ADV7390/ADV7392) OR 0x56 (ADV7391/ADV7393)Please verify you are using the correct device address,For 7393 with ALSB low it should be read = 0x55, write = 0x54. Match against Table 16, Figure 48.We use 8bit I2C addressing not 7bit, Some devices use 7bit addressing which could cause the shift i.e (8 bit address >>1).
If you have I2C equipment from total-phase, please note that they use 7-bit addressing.
Below is a good application please note on that:
7-bit, 8-bit, and 10-bit I2C Slave Addressing – Total Phase
Also refer here https://ez.analog.com/video/w/documents/778/adv739x-hardware-reset