ADV7611 - 640x480p 30Hz and 600x600p @30Hz support

Hello,

I wanted a 640x480p @30Hz input video resolution for my application. I have the required video timing parameters and have generated the EDID for the same. When I probe the signals in FPGA using ILA I am observing that the video from the ADV7611 gives 1200+ data valid (data enable) for a single line. The expected data valid is 640 (as per standard video timing). I tried 640x480 @60Hz and it was giving proper data i.e. 640 valids per line. Hence am not sure if ADV7611 supports 640x480p @30Hz. Similar behavior is observed for 600x600 @30Hz. Could you let me know if 640x480p @30Hz and 600x600p @30Hz resolutions are supported by ADV7611. If yes can you share the register settings for the same.

Thank you,

Ronston

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  • 0
    •  Analog Employees 
    on Aug 10, 2020 7:04 AM 3 months ago

    Hi,

    640x480p@30Hz,600x600@30Hz the pixel clock would be less than 25Mhz. In HDMI mode, video formats with TMDS rates below 25 M pixels/sec require pixel repetition in order to be transmitted over the TMDS link. When the ADV7611 receives this type of video format, it discards repeated pixel data automatically, based on the pixel repetition field available in the AVI InfoFrame. Please refer Page38 at ADV7611 Reference Manual (UG-180)

    HDMI requires a pixel clock above 20MHz.You need to turn on pixel repetition to get the TMDS clock to get the clock high enough to meet HDMI spec.

    Note: Pixel repetition is used to get the TMDS clock above the spec'd minimum of 20MHz.  When using pixel repetition the sink would need to ignore the duplicated pixels to get back down to a original format.  Note the AVI infoframe carries the pixel repetition information so the sink can respond correctly.

    Thanks,

    Poornima

  • Hello Poornima,

    Thank you for the reply.

    From the reply what I understood is that the ADV7611 does not support pixel frequency below 20MHz. Hence when any video with pixel clock below 20MHz is received it divides the clock until the frequency reaches above 20MHz and similarly repeats the input data twice (which is discarded by default). But as I was receiving 1280 valids (approx) instead of 640 can I assume that the repeated data is not being discarded? Will discarding it give me 640 valid data per line but at a clock of 26MHz instead?

    For clarification please consider the following case:

    For 640x480p @30Hz, the input pixel clock is 13MHz. Will the pixel repition done by ADV7611 convert this to 26MHz and then give this clock as output? Or will the clock frequency output from the ADV7611 remain 13MHz itself? And you could also tell me whether the data will remain on the line for 2clock cycles of the output clock ?

    Is there any script for configuring the ADV7611 to 640x480p @30Hz which will give me 13MHz clock and 640 valids? Do you know of any methods which can achieve this without any external help as it would be really helpful if I can generate it using ADV7611.

    Thank and Regards,

    Ronston

  • Hello,

    Sorry I was tied up with some other work.

    Currently I don't want to make any changes to ADV7511 register configuration. I am internally generating the video for the ADV7511 using XIlinx IP's.

    My concern is regarding ADV7611. I am not sure if it was a typo form your side for the following statement

    " Could you please configure the below register in ADV7511 (Did you mean ADV7611) as 72 3b CA."

    Awaiting your confirmation for the same.

    The readback from 68 05 register of ADV7611 should be done after the EDID configuration or before. Just wanted to confirm.

    Thanks and Regards,

    Ronston

  • 0
    •  Analog Employees 
    on Aug 17, 2020 9:13 AM 3 months ago in reply to Ronston

    Hi,

     That is not an typo, If you changed in ADV7511 Tx side, then the source will send the data according to that.

    The readback from 68 05 register of ADV7611 should be done after the EDID configuration or before. Just wanted to confirm.

       After EDID configuration.

    Thanks,

    Poornima

  • Hello,

    I did not update the ADV7511 register configuration. The reason for not updating is that my FPGA RTL code will throw an error if I dont receive the proper resolution and thus no data will be sent to ADV7511 unless I get the required resolution from ADV7611.

    The readback value from the 68 05 register of ADV7611 seems to be varying for different confiurations. I observed values 0x00 and 0xB0 when reading the said register. Will get back to you regarding the same after I confirm if the value is actually varying or not.

    What is the value that you are expecting from this particular read?

    Thanks and Regards,

    Ronston 

  • 0
    •  Analog Employees 
    on Aug 19, 2020 2:03 PM 3 months ago in reply to Ronston

     Hi,

       For all configuration it will remain 68 05[0:3] as "0000" i.e 1x.

       Unless u will change this value in 0x3B and 0x3C in ADV7511, 68 05 will not get updated for 640x480p@30Hz.

       Please note that 'Tooverride the VIC detection, the pixel repeat mode must be set to manual by setting register 0x3B[6:5] to 0b10 or 0b11. The desired VIC is input into 0x3C[5:0]'.

    Thanks,

    Poornima

  • Hi,

    I guess I was not able to explain my application to you clearly and thus there seems to be some misunderstanding.

    I connect my CPU to the ADV7611 through HDMI. The video coming from this is sent to the FPGA. Here packetization is done and sent out through transceiver and looped back. The received data is again sent to FPGA for depacketization.  The depacketized data is converted to video format using Xilinx IP's and then sent to the ADV7511 in YCbCr 422 format. This is then connected to a display using HDMI.

    The FPGA has overflow and underflow error detection. If the input video from the ADV7611 has more valids or less valids per line then these errors are indicated and no data will be sent to ADV7511. The issue here is only at the input side and not at the output. I dont want to add any additional logic in my FPGA code to remove the additional pixels coming from the ADV7611 for resolutions having pixel clock less than 20MHz. 

    So I am not clear as to why the ADV7511 configuration needs to be changed. Were you expecting that whatever data comes from ADV7611 will be sent to ADV7511 without any changes? Sorry but thats not the case here. Hence I dont think I can discard the repeated values at the ADV7511 cause this means I will have to configure my project for 1280x480 resolution instead of 640x480 so as to make sure the repeated values are also sent.

    My requirement is that I want 640 valids only from ADV7611 per line for 640x480p @30Hz resolution. I dont want to receive 1280 valids instead of 640 valids. So is it possible to do so by changing register configuration of ADV7611 only. I cant to do any make arounds with ADV7511 to discard these extra pixels cause it would not satisfy my project requirements. 

    In brief what I want to know is " Can I obtain only 640 valid pixels per line for 640x480p @30Hz resolution from the ADV7611 by changing any register configuration of only ADV7611?"

    Thanks and Regards,

    Ronston

Reply
  • Hi,

    I guess I was not able to explain my application to you clearly and thus there seems to be some misunderstanding.

    I connect my CPU to the ADV7611 through HDMI. The video coming from this is sent to the FPGA. Here packetization is done and sent out through transceiver and looped back. The received data is again sent to FPGA for depacketization.  The depacketized data is converted to video format using Xilinx IP's and then sent to the ADV7511 in YCbCr 422 format. This is then connected to a display using HDMI.

    The FPGA has overflow and underflow error detection. If the input video from the ADV7611 has more valids or less valids per line then these errors are indicated and no data will be sent to ADV7511. The issue here is only at the input side and not at the output. I dont want to add any additional logic in my FPGA code to remove the additional pixels coming from the ADV7611 for resolutions having pixel clock less than 20MHz. 

    So I am not clear as to why the ADV7511 configuration needs to be changed. Were you expecting that whatever data comes from ADV7611 will be sent to ADV7511 without any changes? Sorry but thats not the case here. Hence I dont think I can discard the repeated values at the ADV7511 cause this means I will have to configure my project for 1280x480 resolution instead of 640x480 so as to make sure the repeated values are also sent.

    My requirement is that I want 640 valids only from ADV7611 per line for 640x480p @30Hz resolution. I dont want to receive 1280 valids instead of 640 valids. So is it possible to do so by changing register configuration of ADV7611 only. I cant to do any make arounds with ADV7511 to discard these extra pixels cause it would not satisfy my project requirements. 

    In brief what I want to know is " Can I obtain only 640 valid pixels per line for 640x480p @30Hz resolution from the ADV7611 by changing any register configuration of only ADV7611?"

    Thanks and Regards,

    Ronston

Children
  • +1
    •  Analog Employees 
    on Aug 20, 2020 11:49 AM 3 months ago in reply to Ronston

    Hi,

     This is the only method to increase the pixel clock from source to meet the HDMI spec.

     Unless you can't transmit 640×480@30Hz in HDMI interface.

    Please note that as I already stated,

    Note: Video format with native pixel rates below 25MHZ require pixel- repetition in order to be carried across a TMDS link.

    720x480i and 720x576i video format timings shall always be pixel repeated.
    For pixel repeated formats, this value indicates the number of pixels that may be discarded by the sink without losing real image content.
    640x480p @30Hz has a pixel clock would be less than 25Mhz.HDMI requires a minimum TMDS rate of 20MHz.
    So 640x480p @30Hz can only be transmitted as 1280x480 though HDMI, with a greater pixel clock of 25 MHz.
    You will notice that the LLC clock is 27MHz with the script above please crosscheck.
    If your send 640x480p @60Hz format, there is no issue you will getting output because its pixel clock value is 25.175 MHZ.
    Also i believe 640x480p @30Hz format not an standard format please go through the VESA and CEA documents.

    Thanks,

    Poornima

  • Hi,

    Thank you so much for your help up till now.

    Yes I am working with few non standard video resolutions.

    I understood that 640x480 @30Hz can only be received as 1280x480 @30Hz. I will generate the 640x480p @30Hz and 600x600p @30Hz through a pattern generator.

    I was observing that the display was detecting the video as 1280x480p when I gave 640x480p @60Hz as input to ADV7511. Could you help me check if there is some issue with my register configuration. The ADV7511 configuration is as follows. 

    (Please note that the ADV7511 slave address is not present in the below array. The first byte gives the Register Address and the last byte gives the data written to the particular Register. The input to the ADV7511 is 16-bit YCbCr 422 colorformat.)

    {0x41, 0x00, 0x10},
    {0xD6, 0x00, 0xC0},
    {0x15, 0x00, 0x01},
    {0x16, 0x00, 0x3C},
    {0x18, 0x00, 0xAB},
    {0x19, 0x00, 0x37},
    {0x1A, 0x00, 0x08},
    {0x1B, 0x00, 0x00},
    {0x1C, 0x00, 0x00},
    {0x1D, 0x00, 0x00},
    {0x1E, 0x00, 0x1A},
    {0x1F, 0x00, 0x86},
    {0x20, 0x00, 0x1A},
    {0x21, 0x00, 0x49},
    {0x22, 0x00, 0x08},
    {0x23, 0x00, 0x00},
    {0x24, 0x00, 0x1D},
    {0x25, 0x00, 0x3F},
    {0x26, 0x00, 0x04},
    {0x27, 0x00, 0x22},
    {0x28, 0x00, 0x00},
    {0x29, 0x00, 0x00},
    {0x2A, 0x00, 0x08},
    {0x2B, 0x00, 0x00},
    {0x2C, 0x00, 0x0E},
    {0x2D, 0x00, 0x2D},
    {0x2E, 0x00, 0x19},
    {0x2F, 0x00, 0x14},
    {0x48, 0x00, 0x08},
    {0x55, 0x00, 0x00},
    {0x56, 0x00, 0x28},
    {0x98, 0x00, 0x03},
    {0x9A, 0x00, 0xE0},
    {0x9C, 0x00, 0x30},
    {0x9D, 0x00, 0x61},
    {0xA2, 0x00, 0xA4},
    {0xA3, 0x00, 0xA4},
    {0xAF, 0x00, 0x04},
    {0xE0, 0x00, 0xD0},
    {0xF9, 0x00, 0x00}

    Note: I tried doing manual pixel repeatition and manual VIC. But the output video was cropped out and I was not able to get the exact video. I updated the 0x3B register with 0x40 and 0x3C with 0x01. This register configuration is not reflected in the register settings shown above. 

    Thanks and Regards,

    Ronston

  • 0
    •  Analog Employees 
    on Aug 21, 2020 11:45 AM 3 months ago in reply to Ronston

    Hi,

     Please note that a Sink that supports 640x480p @ 59.94/60Hz shall support video formatted in a 4:3 Picture Aspect Ratio i.e 640x480 format, which is always sent as 4x3 data, and is rendered according to the characteristics of the Sink.

    For manual pixel repetition configure 0x3b as 0xCA and 0x3C as 0x0E.

    Thanks,

    Poornima