I am doing static timing analysis on the I2C interface of the ADV7180 to a Xilinx SoC. Most of the timing parameters I need are provided in the ADV7180 datasheet, except for data output hold time.
In other device datasheets, I have seen this parameter referred to as "clock to data delay time" or "output valid from clock" and is typically specified as 900nsec max.
The closest spec in the ADV7180 datasheet is "Hold Time (Start Condition)" at 600ns min, but the max is not specified, and this is specifically calling out the start condition, not the "normal" condition.
Any help or suggestions would be appreciated.
We generally don't state maximum hold times of our devices. This is because our devices (like the ADV7180) are I2C slaves. The I2C master must keep the data high after the SCLK pulse for at least…
Your question has been forwarded to the part specialist and you will get an update soon
We generally don't state maximum hold times of our devices. This is because our devices (like the ADV7180) are I2C slaves. The I2C master must keep the data high after the SCLK pulse for at least the hold time specified in the datasheet. This gives our part time in order to clock in the I2C data. If the I2C master want to keep the data there longer than the specified hold time then that is fine. From our parts point of view there is no such time as a hold time that is too long.
Saying that you I2C Master will still need to keep the setup time specification for the next I2C pulse.
The minimum hold time specified during start-up is 600 ns. You are correct that the minimum hold time specified during normal operation is not specified. Apologies this is an oversight in our datasheet. I believe that the minimum hold time during normal operation is 100 ns. I will double check this with our design team and get back to you ASAP.
Thanks and Regards,
Senior Applications Engineer,
Analog Devices Inc.