I use ADV7619.I am trying to configure a resolution of 1600x1200p 120Hz (VESA DMT ID: 38 h).But the ADV7619 is not operates well.(1600x1200p 60Hz is well. 2 x 24 bit RGB 444 Out)
LLC : output DE : output HS : not well (Low) VS : not well (Low) P[47:24] : output (?) P[23:0] : not well
Setting ValueSince the TMDS clock is 268.25 MHz (> 170 MHz), the following samples are set.ADV7619 Design Support files : ADV7619-VER.1.9c.txt ##03 HDMI Input to ADV7619, Input Pixel Frequency > 170MHz ## :03-01 RGB 444 In - 2x24-bit RGB 444 Out - For use up to 4k2k:
About this sample setting, I have 3 questions.
[Q.1]UG-237 (the bottom note on p26) describes the following.OP_FORMAT_SEL[7:0], IO, Address 0x03[7:0] The 0x54, 0x94, 0x95, 0x96 modes registers should be set as follows: (1)DPLL Map, Register 0xC3 to Register 0x80. = 4C C3 80 (2)DPLL Map, Register 0xCF to Register0x03. = 4C CF 03 (3)IO Map, Register 0xDD to Register 0xA0. = 98 DD A0 (4)IO Map, Register 0xBF = 0 (CP_COMPLETE_BYPASS_IN_HDMI_MODES disabled).(In the sample settings of ADV7619-VER.1.9c, OP_FORMAT_SEL=0x54 ; 2x24 bit SDR 444 interleaved mode 0)
However, the following two points are different from the sample settings. (3)98 DD A0 --> sample settings : 98 DD 00 (4)IO Map, Register 0xBF = 0 --> sample settings are none
What is the correct setting?
[Q.2]In the 1600x1200p 120Hz (VESA DMT ID:38h) standard, HS=positive polarity and VS=negative polarity.Can the polarity of the sync signal be received with the sample setting unchanged?Or do I need to change the polarity of the HDMI input?
[Q.3]Are there any other settings I need?
ADV7619-VER.1.9c.txt##03 HDMI Input to ADV7619, Input Pixel Frequency > 170MHz ##:03-01 RGB 444 In - 2x24-bit RGB 444 Out - For use up to 4k2k:98 FF 80 ; I2C reset98 F4 80 ; CEC98 F5 7C ; INFOFRAME98 F8 4C ; DPLL98 F9 64 ; KSV98 FA 6C ; EDID98 FB 68 ; HDMI98 FD 44 ; CP68 C0 03 ; ADI Required Write98 00 19 ; Set VID_STD98 01 05 ; Prim_Mode =101b HDMI-Comp98 02 F2 ; Auto CSC, RGB out, Set op_656 bit98 03 54 ; 2x24 bit SDR 444 interleaved mode 098 05 28 ; AV Codes Off98 06 A0 ; No inversion on VS,HS pins98 0C 42 ; Power up part98 15 80 ; Disable Tristate of Pins98 19 83 ; LLC DLL phase98 33 40 ; LLC DLL MUX enable98 DD 00 ; ADI Required Write98 E7 04 ; ADI Required Write 4C B5 01 ; Setting MCLK to 256Fs4C C3 80 ; ADI Required Write4C CF 03 ; ADI Required Write4C DB 80 ; ADI Required Write68 C0 03 ; ADI Required write68 00 08 ; Set HDMI Input Port A (BG_MEAS_PORT_SEL = 001b)68 02 03 ; ALL BG Ports enabled68 03 98 ; ADI Required Write68 10 A5 ; ADI Required Write68 1B 00 ; ADI Required Write68 45 04 ; ADI Required Write68 97 C0 ; ADI Required Write68 3E 69 ; ADI Required Write68 3F 46 ; ADI Required Write68 4E FE ; ADI Required Write 68 4F 08 ; ADI Required Write68 50 00 ; ADI Required Write68 57 A3 ; ADI Required Write68 58 07 ; ADI Required Write68 6F 08 ; ADI Required Write68 83 FC ; Enable clock terminators for port A & B 68 84 03 ; FP MODE68 85 10 ; ADI Required Write 68 86 9B ; ADI Required Write 68 89 03 ; HF Gain68 9B 03 ; ADI Required Write68 93 03 ; ADI Required Write68 5A 80 ; ADI Required Write68 9C 80 ; ADI Required Write68 9C C0 ; ADI Required Write68 9C 00 ; ADI Required WriteEnd
If Possible, Could you please crosscheck with our eval board ?
Due to COVID, We don't have hardware to verify in our side now.
Q1) Set below registers according to UG-237 instead of sample setting. DPLL Map, Register 0xC3 to Register 0x80. DPLL Map, Register 0xCF to Register0x03. IO Map, Register 0xDD to Register 0xA0. IO Map, Register 0xBF = 0 (CP_COMPLETE_BYPASS_IN_HDMI_MODES disabled).
Q2) Change the polarity of the Hs,Vs signals according to VESA DMT in 0x06 register.
Also refer Table 83 for 2x24-bit RGB 444 Out pixel output pins and let us know.
Hi PoornimaThank you for the reply.
I tried your settings but it didn't display well.I have additional questions.
[Q.1]IO Map, Register 0xBF = 0 (CP_COMPLETE_BYPASS_IN_HDMI_MODES disabled).What should the bits(0xBF[7:1]) other than 0xBF be set to?Should I set it to "98 BF 00" ?
[Q.2]I changed the register(IO Map 0x06), but the HS,VS signal was only inverted. HS : not well (Fix Low -> Fix High) VS : not well (Fix Low -> Fix High)However, when the HDMI output polarity of the video card was set to positive polarity for both HS and VS, sync outputs well.Is this behavior correct?But the data(P[23:0]) has not yet been output well.
Also 2x24bit RGB444 Out of 1600x1200p 60Hz is operates well.Therefore, I think the output pin settings are correct.
Yes,it should be "98 BF 00"
The remaining bits are not documentated for 0xBF IO Map.
Please let us know, whether you are using 8/10/12 bit - 1600x1200p120Hz?
I'm using 8bit 1600x1200p120Hz.