To whom it may concern,
I have a product in market which transfers data between ADV7511 and ADV7612.
There are problems which i didn't notice before,
1. Sometimes the image becomes dark, means image data from ADV7511 becomes dark image(zero)
after passing ADV7612.
2.Sometimes the image becomes noisy(snow like noise).
To come to a solution please refer to the questions below,
1.About data transfer improvement, are there any registers that i can change settings to
improve data transfer between ADV7511 and ADV7612?
2.In ADV7511 side, are there any registers for de-emphasis?
3.In ADV7612 side,about the stability of PLL lock signal. How can i relax the
pull-in range for PLL lock signal due to the input clock jitter? And how much
jitter in the input clock can the pll lock pull-in range be relaxed?
Please it's urgent since the product is already in market.
Yes, these registers explanation is not present in programming guide. Please use the script recommended value.
72 9C 30 ; PLL filter R1 value72 E4 60 ; VCO_Swing_Reference_Voltage
About data transfer improvement, are there any registers that i can change settings to
Please crosscheck the pixel bus mapping, Y pins that don't exist on the 7611 and those that do come out would produce a darker image.Check with spread sheet of 7842 output port. The same output mapping is used in the 7611 however you have to use this judiciously since the 7842 has 36 output pins and the 7611 has only 24 pins. Also make sure the Y bit pin muxed to the wrong pin in the processor in that case we will lose the most significant value.
Please refer here https://ez.analog.com/video/f/q-a/10027/adv7611-dvi-1024x768-input/32043#32043
In ADV7511 side, are there any registers for de-emphasis?
The scripts provided with the devices are optimized for cable settings as per HDMI specifications.
Please refer here https://ez.analog.com/video/f/q-a/6426/how-do-you-set-pre--or-de-emphasis-on-video-transmitter/20914#2091
And how much jitter in the input clock can the pll lock pull-in range be relaxed?
Refer here https://ez.analog.com/video/f/q-a/7502/adv7182-in-crystal-mode/15568#15568
Thank you for your reply.
About data transfer improvement between ADV7511 and ADV7612
Sometimes(once or twice in an hour) i get no image (including sync signals) from ADV7612.When this happens, i look at the inputs of ADV7612 and the inputs are there. So are there any registers i can change in order not to get this behaviour.
About the stability of PLL lock in the ADV7612
How can i get stable PLL lock status after a small amount of jitter in the incoming TMDS clock? Means PLL not to unlock due to small amount of jitter in the TMDS clock.
Please go with latest script rev 3.0 is dated on 2014 i.e 72 DE D8
Also refer here https://ez.analog.com/video/f/q-a/6275/adi-recommended-write-in-adv7612-ver-3-0c-script
Thank you for your quick response.
From the latest script rev 3.0, there are registers for setting VCO swing reference voltage 72 E4 and PLL filter R1 value 72 9C.
I don't see explanations for these registers in the programming guide. Are there any other values for these registers?
After trying different values for 72 E4, i started getting better results but no solution yet.
You helped me alot for your quick and precise answers.
Good to know, Please make sure with one more writes for VCO_Swing_Reference_Voltage
0x72, 0xE4, 0x60 // VCO_Swing_Reference_Voltage
0x72, 0xF9, 0x00 // VCO_Swing_Reference_Voltage