ADV7280A I2C problem

Hi,

  As per recommended script, the normal sequence would be follow as like below, Please make sure with your i2c writes,

     delay 10;  // wait 10ms after hardware reset to start i2c
     42 0F 80; // Reset Decoder(ADV7280A) - Chip reset for loading all I2c bits with default values (This bit is self clearing one, approximately it take 2ms for reset)
    delay 10;  // wait another 10ms
    42 0F 00;  Exit power down mode[ADV7280A writes begin]

Note :Generally after ADV728x-M is programmed, the clock lanes should exit low power mode and it remains in high speed mode until the part is reset  or powered down.
In the ADV7280 rev.A datasheet the simplified power-up sequence  state that a software reset is needed after power-up.
After the hardware reset wait 10 ms before beginning I2C communication. Not performing the hardware reset can leave the ADV7280 in a state where it is not able to perform I2C communication properly.

 Please refer here for more details about I2C https://ez.analog.com/video/w/documents/15352/i2c-protocol-sequence

Thanks,

Poornima 

Hi,

  As per recommended script, the normal sequence would be follow as like below, Please make sure with your i2c writes,

     delay 10;  // wait 10ms after hardware reset to start i2c
     42 0F 80; // Reset Decoder(ADV7280A) - Chip reset for loading all I2c bits with default values (This bit is self clearing one, approximately it take 2ms for reset)
    delay 10;  // wait another 10ms
    42 0F 00;  Exit power down mode[ADV7280A writes begin]

Note :Generally after ADV728x-M is programmed, the clock lanes should exit low power mode and it remains in high speed mode until the part is reset  or powered down.
In the ADV7280 rev.A datasheet the simplified power-up sequence  state that a software reset is needed after power-up.
After the hardware reset wait 10 ms before beginning I2C communication. Not performing the hardware reset can leave the ADV7280 in a state where it is not able to perform I2C communication properly.

 Please refer here for more details about I2C https://ez.analog.com/video/w/documents/15352/i2c-protocol-sequence

Thanks,

Poornima 

Hello Poornima,

I am facing problem in getting acknowledgment for I2C to start writing the data,

Referring to your answer, I have given sufficient delay (>20ms) after power on reset before starting the I2C.

PoornimaSubramani said:

42 0F 80; // Reset Decoder(ADV7280A) - Chip reset for loading all I2c bits with default values (This bit is self clearing one, approximately it take 2ms for reset)

To do this means writing data 80  to I2C address 42, device should respond for register address and give acknowledgment for write request on 9th clock cycle, which is missing.

What may be the reason for this?

Hi,

 Please make sure you have the right address, a lot of software defines I2C addresses as 7-bit addresses(i.e In that case we need to right shift the 8 bit map address to one),our i2c driver work with 8-bit address.

 Do you have one of our evaluation board ? If not,Please crosscheck your schematic with 0676.ADV7280Schemaic.zip

Here you can find the more details about i2c bus specification and also timing related details I2C Bus Specification and User Manual

https://i2c.info/i2c-bus-specification

Note :In order to initiate communications, the master transmits a start condition followed by the 8 bit address of the slave device. When a peripheral recognizes the address. it transmits an acknowledgment by pulling the SDA line low. By transmitting a byte of data or an address takes eight clock cycles,master generates all clock pulses, including the acknowledge ninth clock pulse.
During acknowledge clock pulse during which the receiver must pull the SDA line low and keep it low during the High period of the clock in order to acknowledge the previous byte or address.But SDA remains HIGH during this ninth clock pulse, this is defined as the Not Acknowledge signal
If the slave is not ready to receive more data it may produce a no acknowledge by leaving the line high.
This will cause the master to either abort the transfer by producing a stop condition or suspend the transfer by producing a repeated start.

Thanks,

Poornima

Hello Poornima,

I am controlling the I2C from FPGA and a vhdl code is written to work as per i2c specifications and the code was tested with  other i2c devices and working fine.

 As per your note and also my initial query is all about getting ack at ninth clock cycle, which i am not getting and the schematic is fine w.r.t eval board schematic, only change is i am using 1.8V for all supply including i2c levels.

 Regarding using the correct address, address can be either 0x40 or 0x42 only, both are tried.

 Please suggest why device is not acknowledging.

Thanks

Arun