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About ADV7850



		

			

									
						michaelyoung00
					
							

			
				
									
											
							 		
		        	            							
			
			    	
			                    
                
				                on Mar 13, 2020 
				
			
			
		


				
		

		    		    
		    
		    	
			
Hi,


    I have an issue about ADV7850, symptom as described below:


   Now we utilize ADV7850 to develop a ADC to HDMI Box (VGA, YPbPr, S-Vide0, CVBS input), and we have designed our board and follow our distributor to fill the register but we can't display our image correctly. Phenomenon as below:


1. In some timing (such as 1920x1080 VGA) , we can't see the far left 1 pixel, but if we move the picture to right, this pixel still disappear and also the far right 1 pixel disappear.




2 in some timing,  we can't see the top 1 pixel but if we move the picture to downward, this pixel still disappear and the far bottom 1 pixel will also disappear.




Could you help us which register we can adjust to correct this issue.




Thanks.


Michael

								


				
				
		

			
						
									
									
						
						
			
			
			
			
		


					

			





	










	

	

					



			


				
	









	
    
	

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                                 Analog Employees 
                                
                            
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                on Mar 13, 2020 12:53 PM
            
            
					
    
	
    

		
		
    
					
    Hi,
    

    This type of issue might be caused by the H & V sync width and placement in relationship to the active video.You can tweak to the sync pulses relative to the input sync pulses and active video. Start with sdp_hs_beg_adj, sdp_hs_end_adj and sdp_hs_width registers to move the HSync around.Same applies to the VSync for cutting off lines.

    There are ways to move the VS/Hs edges like register start_vs and end_vs but theses only move the edges by +-8 lines. 
    Generally you do not have to do this either since the source will generate the correct VS and HS signals.
    And Also try to adjust the data enable bit de_h_end,de_h_start,de_v_start[5:0],de_v_end[5:0]

    Note : The conversion between, Analog to HDMI, a DE signal needs to be generated and it should transmitted with the HDMI data.
    The ADV7850 generates a DE signal based on the HS and VS input timing. If for any reason, this is non-standard , the DE output may be nonstandard also.
    

    

    Thanks,
    

    Poornima
    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
						
						
				
				
		
		
    
			
		
    
	
    

    

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