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ADV7619 HPA hardware failure

Hi all!

We've a custom hardware using a ADV7619 in prototyping stage where the second board just failed due to HPA not going high. (It was working for some time.) I'd like to find out why that happens. Our schematic followes the reference design (RXA_5V via 1k to HPA_A, RXA_5V and HPA_A directly connected to ADV, HPA connected to external ESD protection). On the dead hardware we found, that HPA does not raise above 1.7V. If we cut the wire between the 1k and HPA, HPA raises (because its not controlled by the ADV anymore) but SDA is kept low.

The register programming does not follow the recommendations yet. We've configured HPA_AUTO_INT_EDID to mode 2 (HPA goes high if EDID is active and after cable detect delay, HDMI reg 0x6C, bits 1 and 2) and disable the DDC/EDID via Repeater reg. 74 bits 0 and 1 while changing the EDID memory.

Does anymore have an idea why HPA does not work in our setup?

Best regards

Pauliman

Top Replies

  • FormerMember
    FormerMember
in reply to Pauliman +1 verified

I can't add anything more then what is stated in the data sheet.

Another approach to this is to put a 33 Ohm resistor in series with each of the pins in question.  The 33 Ohms won't interfere with their…

  • FormerMember
    0 FormerMember

Normally HPA is pulled to DDC_5V with a 1K resistor at the source and weakly pulled high with a 47K resistor at the sink.  The ADV7619 HPA pin is an open drain pin only.   It's weakly pulled high at the sink to keep the HPA pin from floating when the cable is not connected.

From your description it does appear the HPA pin is damaged.  You would have to run failure analysis on the part to figure out exactly what the failure is. (Contact your local FAE about going down this path.)

What can cause this problem, (just listing the possibilities, not stating this is what happened)

1) Bad or wrong ESD protections

2) Possible power up sequence difference between the source and sink, where the HPA line has voltage applied to it before the sink to source grounds are connected.  This might cause current surges going through strange paths.

3) At one point of the HPA operations it was asked to sink more current than the specs allowed for damaging the HPA open drain FET.

What ESD protection devices are you using?

  • Hi GuenterL!

    Many thanks for your response. We followed the reference design (1k between DDC_5V and HPA, 47k between DDC_5V and DDC_SCL, CEC via 22k and diode on system 3V3, HPA, DDC_5V, DDC_SDA and DDC_SCL directly connected to the ADV, use a WE 685119134823 HDMI connector with pin 17 - and others - on GND, shield is open) but installed a TPD4E1U06 ESD diode.

    Yes, we powered the ADV and the source up and down in any order and connected the cable with ADV powered up as well as down.

    Today I tested the damaged boards again and found again, that HPA is not going high. Its kept below ~1.6V by the ADV. I also found, that DDC_SDA seems to be damaged as well. I can see a signal, but only at 0.2..0.4V. So it seems, that the ADV is keeping DDC_SDA low as well.

    Can you provide limiting values for the pins, that are connected to the HDMI input (DDC_5V, HPA, DDC_SCL, DDC_SDA and CEC)?

    Best regards

    Pauliman

  • FormerMember
    +1 FormerMember in reply to Pauliman

    I can't add anything more then what is stated in the data sheet.

    Another approach to this is to put a 33 Ohm resistor in series with each of the pins in question.  The 33 Ohms won't interfere with their normal operation but it can reduce any ESD hits or max current dissipations if they occur.  

    From my past experience, damage like this is often caused by burning through the gate oxide or damaging the internal ESD protection on the pin.  The only sure way to know is to have the part go through Failure Analysis where we take the lid off and looks at the silicon directly.  

  • Many thanks GuenterL! We'll try the series resistors with our next prototype.