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AD9889 Y & C components swapped

I have the AD9889 HDMI transmitter working properly in HD modes (1080i, 720p) with 16-bit YCrCb data.

I am having problems, however, getting 480p mode working with 8-bit YCrCb data (input_ID 4).  I get a display, but the Y and Cr/Cb components are swapped.  I am sending a standard ITU-656 video stream (ie: Cb, Y, Cr, Y), with the DE signal asserted along with the first valid data (Cb compnent of the first pixel).  In crude ascii art:

DE   : 0  0  1  1  1  1  1  1 ... 1  1  1  1  1  1  0  0
Data : xx xx Cb Y  Cr Y  Cb Y ... Cr Y  Cb Y  Cr Y  xx xx

I haven't found any timing diagrams of DE vs. data for the 8-bit 4:2:2 video input modes, nor have I found any register settings that allow swapping of the components.  Can you tell me if I need to adjust a register setting or two, or perhaps change the DE timings when running in input_ID 4 (8-bit 4:2:2 video with separate syncs)?

If it helps, following is a register dump of the part when it is transmitting 480p, input_ID 4, with swapped Y and Cb/Cr compoonents:

0x00 = 0x00 0x00 0x18 0x00 0x00 0x69 0x78 0x00
0x08 = 0x00 0x00 0x01 0x0e 0x06 0x18 0x01 0x13
0x10 = 0x25 0x37 0x00 0x00 0x00 0x26 0x70 0x0a
0x18 = 0x08 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x20 = 0x00 0x00 0x08 0x00 0x00 0x00 0x00 0x00
0x28 = 0x00 0x00 0x00 0x00 0x08 0x00 0x00 0x00
0x30 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x38 = 0x00 0x00 0x00 0x81 0x00 0x03 0x0c 0x00
0x40 = 0x40 0x10 0xe0 0x7e 0x78 0xae 0x68 0x80
0x48 = 0x00 0x00 0x04 0x38 0x00 0x00 0x07 0x80
0x50 = 0x00 0x00 0x4e 0x65 0x77 0x54 0x65 0x6b
0x58 = 0x00 0x00 0x58 0x44 0x38 0x35 0x30 0x00
0x60 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x68 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x70 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x78 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x80 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x88 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x90 = 0x00 0x00 0x00 0x00 0x84 0xc0 0x30 0x00
0x98 = 0x03 0x02 0x00 0x18 0x38 0x61 0x10 0x00
0xa0 = 0x00 0x00 0x87 0x87 0x08 0x04 0x00 0x00
0xa8 = 0x00 0x00 0x00 0x40 0x00 0x00 0x40 0x16
0xb0 = 0x01 0xb8 0x59 0x34 0xa9 0x88 0x95 0xe5
0xb8 = 0xb0 0x00 0x60 0xff 0x00 0x00 0x00 0x00
0xc0 = 0x00 0x00 0x00 0x00 0x00 0x10 0x14 0x00
0xc8 = 0x02 0x03 0x00 0x01 0x02 0x00 0x00 0x70
0xd0 = 0x70 0x70 0x70 0x70 0x70 0x70 0x70 0x70
0xd8 = 0x70 0x70 0x70 0x70 0x70 0x70 0x70 0x70
0xe0 = 0x70 0x70 0x70 0x70 0x70 0x70 0x70 0x70
0xe8 = 0x70 0x70 0x70 0x70 0x70 0x70 0x70 0x70
0xf0 = 0x70 0x70 0x70 0x70 0x70 0x70 0x70 0x70
0xf8 = 0x70 0x70 0x7d 0xaa 0x1c 0x00 0xb0 0x00
  • The same clock that is used to capture data is used to capture the DE.  Is it possible that the DE is transitioning on the same clock edge you are using to capture data?  If this is the case moving the DE signal one clock earlier would resolve the issue.  There is no regsiter setting in the AD9889 to swap the Y and Cr/Cb, so your best option is to modify the DE signal if you are able to.

  • I think input_ID=4 requires embedded syncs.  You say you are using separate syncs which is actually input_ID=3.  Are you actually using embedded syncs and that is a typo?

  • The data and DE signals transition at the same time.  The clock signal transitions 90 degrees offset from the data (for potential use of the DDR modes), and changing the clock polarity does not affect anything.

    I need to know when the DE signal should be asserted (and de-asserted) in relation to the 8-bit 4:2:2 input stream.

  • It is a typo.  I have tried embedded syncs (input_ID 4), but have generally not had luck with embedded sync in either ED or HD modes, so have been using separate sync mode (input_ID 3 for ED and input_ID 1 for HD).

  • You are supplying H and V right?  Have you considered simply using the built in DE generator based on your H and V synchs instead of your DE?  This would eliminate the chance of your DE timing making a difference.

    Table 24 of the Programming Guide has values for this for various CEA 861B formats.

  • Sorry for the delay, I was on vacation and just got a chance to try this.

    I /do/ manage to get the monitor to sync to the output when running with DE generation enabled, but the signal is still green (Y and Chroma components still swapped).  I supsect this is due to the fact that the H/V timings are similar to my generated DE (ie: change at the same time as the Cb data is driven).

    I also tried again to get the embedded TRS mode 4 working for ED mode (720 x 480p), but had no luck so am sticking with external H/V/DE mode 3.

    I really just need some documentation on how to phase the H/V/DE signals when running in 8-bit 4:2:2 mode with a 2x clock, or maybe a register dump of the part setup in embedded sync mode so I can see what I might be doing wrong.  Ideally, I'd like to use the embedded TRS codes like we're sending to the ADV7393, but for some reason I can't get these working for the AD9889. 

    We're currently driving the AD9889 from an FPGA, so I can pretty easily get the proper signal phasings if I know what they're supposed to be...

  • I never heard back on the proper DE to Cb/Y/Cr/Y data phasing to get input mode 3 working, but have bypassed the issue by using input mode 4 (embedded TRS codes), which is preferrable anyway.

    The issue I was having with getting any embedded TRS modes working was due to a bug in the provided Analog Devices example SW driver for the AD9889.  Specifically, the I2C macros called by the set_sync_params (ADI89_SET_VFE_HS_PLA, ADI89_SET_VFE_HS_DUR, ADI89_SET_VFE_VS_PLA, & ADI89_SET_VFE_VS_DUR) ALL referenced the SAME I2C register address (0x30), instead of the proper register values (ie: 0x30, 0x31, 0x32, & 0x33).  Once I fixed this and loaded proper values for the sync generation logic, everything started working!

  • Well that is good news!

    I'm sorry we were not able to get you the particular timings you were looking for faster, but at least you have it sorted. 

  • This question has been closed by the EZ team and is assumed answered.