AD9252 LVDS interface


I am planning to use AD9252, and I have few questions:

1. Loooking at the data sheet page 5 table 3 Innput common mode voltage is says typical 1.2V, but when I search for LVDS oscilator, all of them are 1.25V will those 50mV create a problem?

2. Data sheet is not specifying Typ./Max Differential Input voltage for the clock, can you please provide this data?

3. Do I need to have any termination resistors on clock lines?

4. I am planning to sample input signal with 40MHz frequency, but data sheet is calling everywhere for 50 Mhz, will it create problem?

  • 0
    •  Analog Employees 
    on Jun 18, 2010 1:49 AM


    1) Not likely, however most customers use AC coupling caps between the two in order to break the common mode bias differences.

    2) No greater than the absolute max rating of +3.9V.

    3) Yes for LVDS and PECL this sets up the proper bias and swing.

    4) The min clock rate is 10MSPS so a 40MHz sample rate is fine.

    Figure 20 in the data sheet shows performance over clock rate as well.


  • 0
    •  Analog Employees 
    on Aug 2, 2018 4:11 PM
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin