ADV7181C SVGA issues

Hello,

In our application we are using the ADV7181C to handle a number of different video types, from composite NTSC to RGB and high resolution RGB.

The NTSC type video works fine at all temperatures, the issue we are seeing is related to the 800x600 pixel @60Hz SVGA video.

At room temperature, there is a very slight pixel disturbance on the video output, on the right hand edge of the screen.

At -40C (yes we operate at that temperature) the output video is severely distorted. The right hand edge has a mouse teething pattern, similar to a bad de-interlacing algorithm. There are also areas of video where there is green video, even though it should be colour bars (white is on the right hand edge of this pattern). As the temperature increases, upto around ambient, the problem is most noticable.

The current decoder settings are attached.

The incoming video is fed to the decoder by an AD8130 configured as a differential input buffer and is AC coupled to the ADV7181C.

The system uses Sync-on-green and the circuit shown in the ADV7181C manual has been used verbatim.

The power supplies are stable and filtered. The 28.6363 MHz crystal is a 30ppm part that starts properly at -40.

The video output is 16 bit video that goes to a downstream FPGA which processes the video to then feed it to a GPU.

As a test, we configured the decoder to 'free-run' and output the default blue screen. This was stable and none of the noise artefacts were discernable.

This has led us to look at the analogue input stage and sampling mechanism.

Any suggestions of possible changes to improve the stability of the system?

Ian

svga_sample.txt.zip
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  • Hi Guenter,

    With regard to the PWRDWN signal, I can control this from my ADM1064 power sequencer device. Will test this next week.

    We wait 10ms after an I2C reset before writing additional commands to the device.

    I could not publish the schematics in a public forum. They are based on the ADV7181C reference design.

    Perhaps a better way to describe the problem is to show you the resultant video image.

    On power on the image in cold_capture_2.png was taken, it looks like the GPU is not locking onto all the data.

    Once the unit has warmed up, the image in cold_capture.png was acquired.

    Once the unit has warmed up to around 5C, it behaves normally.

    The PCB is conformally coated with 1B31 humiseal.

    Setting up some tests next week to ensure that the HSYNC/VSYNC signals are active and that they do not wander.

    Many regards,

    Ian

    attachments.zip
Reply
  • Hi Guenter,

    With regard to the PWRDWN signal, I can control this from my ADM1064 power sequencer device. Will test this next week.

    We wait 10ms after an I2C reset before writing additional commands to the device.

    I could not publish the schematics in a public forum. They are based on the ADV7181C reference design.

    Perhaps a better way to describe the problem is to show you the resultant video image.

    On power on the image in cold_capture_2.png was taken, it looks like the GPU is not locking onto all the data.

    Once the unit has warmed up, the image in cold_capture.png was acquired.

    Once the unit has warmed up to around 5C, it behaves normally.

    The PCB is conformally coated with 1B31 humiseal.

    Setting up some tests next week to ensure that the HSYNC/VSYNC signals are active and that they do not wander.

    Many regards,

    Ian

    attachments.zip
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