ADV7181c

Hi all,

         I am new to the Engineer Zone.

         I am currently working on a system which takes in CVBS(preferred) or VGA(less preferred) video input and converts it to 12-bit DDR 4:4:4 RGB output. I am using ADV7181c for this purpose. I hope that this chip is capable of doing that.

        The control to the chip is through Xilinx FPGA XC3S500E mounted on Digilent Nexys 2 board. I want to know what exactly are the registers in the chip that are to be configured/programmed to get this operation going?

        Also any ideas on how to actually create an I2C controller in FPGA which will configure the chip in the bginning of its operation? Means FPGA is the master here, and ADV7181c is the slave. The SCL clock will be generated by FPGA at 400 KHZ. On the SDA line, after the Start bit, one by one the (starting from MSB) the slave address, followed by acknowledge from slave, followed by register sub address, followed by ack from slave and finally data to be written will be sent, followed by ack form slave - am I right about the sequence?

       Please reply quickly to this post. Help is urgently required.

ADV7181C_Manual_RevC.pdf
  • 0
    •  Analog Employees 
    on Mar 28, 2011 4:47 PM

    Hello Debs,

    First of all welcome to the Engineering Zone or EZ for short.  The 7181 should be applicable to your requirements.

    This link provides all the information for the 7181 including the script files to control the part.  The script files are just a sequence of I2C commands which any I2C master can send to the device.  You can tweak the scripts as needed.  Check the following link:

    http://ez.analog.com/docs/DOC-1621

    For the I2C controller in the FPGA, I'm sure Xilinx has a small 8 bit controller module and a I2C module that can be compiled into the code.  I'm very familiar with Lattice and for that part we had a CPU core, I2C controller and some C code to generate the bit stream.  Any small low cost microcontroller can accomplish the I2C control also.

    The FAQ link has all the released information on the part.  Let us know what else you need

    Guenter

  • 0
    •  Analog Employees 
    on Aug 2, 2018 4:20 PM
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin
  • ADV7181C_ADV7181C@_ADV7341-VER.8bit-Out-Encoder.txt
    ##CP 525i##
    :525i/60Hz YPrPb In 8Bit 422 EAV/SAV out Encoder:
    42 05 00 ; Prim_Mode =000b for SD-M
    42 06 0A ; VID_STD=1010b for SD 4x1 525i
    42 1D 47 ; Enable 28MHz Crystal
    42 3A 11 ; Set Latch Clock 01b, Power Down ADC3
    42 3B 81 ; Enable internal Bias
    42 3C 52 ; PLL_QPUMP to 010b
    42 67 13 ; DPP Filters
    42 6B C3 ; Select 422 8 bit YPrPb out from CP
    42 7B 06 ; clears the bits CP_DUP_AV and AV_Blank_EN 
    42 85 19 ; Turn off SSPD and force SOY. For Eval Board.
    42 86 1B ; Enable stdi_line_count_mode
    42 8F 77 ; FR_LL to 1820 & Enable 28.63MHz LLC
    42 90 1C ; FR_LL to 1820
    42 BF 06 ; Blue Screen Free Run Colour
    42 C0 40 ; default color
    42 C1 F0 ; default color
    42 C2 80 ; Default color
    42 C5 01 ; CP_CLAMP_AVG_FACTOR[1-0] = 00b
    42 C9 0C ; Enable DDR Mode
    42 F3 07 ; Enable Anti Alias Filters on ADC 0,1,2
    42 0E 80 ; ADI Recommended Setting
    42 52 46 ; ADI Recommended Setting
    42 54 00 ; ADI Recommended Setting
    42 F6 3B ; ADI Recommended Setting
    42 0E 00 ; ADI Recommended Setting
    56 17 02 ; Software Reset 
    56 00 FC ; Power up all DAcs and PLL
    56 01 80 ; SD only mode, Data input on Y-bus
    56 80 10 ; SSAF Luma filter enabled, NTSC mode
    56 82 C9 ; Step control on, pixel data valid, pedestal on, PrPb SSAF on,CVBS/YC out.
    56 84 06 ; RTCO/SFL Enable
    56 88 00 ; 8 bit input enabled
    56 87 20 ; Encoder PAL/NTSC auto-detect enabled
    End
    
    
    
    ##CP 525i##
    :525i/60Hz RGB In 8Bit 422 EAV/SAV out Encoder:
    42 05 00 ; Prim_Mode =000b for SD-M
    42 06 0A ; VID_STD=1010b for SD 4x1 525i
    42 1D 47 ; Enable 28MHz Crystal
    42 3A 11 ; Set Latch Clock 01b, Power Down ADC3
    42 3B 81 ; Enable internal Bias
    42 3C 52 ; PLL_QPUMP to 010b
    42 52 00 ; Colour Space Conversion from RGB->YCrCb
    42 53 00 ; CSC
    42 54 12 ; CSC
    42 55 90 ; CSC
    42 56 38 ; CSC
    42 57 69 ; CSC
    42 58 48 ; CSC
    42 59 08 ; CSC
    42 5A 00 ; CSC
    42 5B 75 ; CSC
    42 5C 21 ; CSC
    42 5D 00 ; CSC
    42 5E 1A ; CSC
    42 5F B8 ; CSC
    42 60 08 ; CSC
    42 61 00 ; CSC
    42 62 20 ; CSC
    42 63 03 ; CSC
    42 64 D7 ; CSC
    42 65 19 ; CSC
    42 66 48 ; CSC last
    42 67 13 ; DPP Filters
    42 6B C3 ; Select 422 8 bit YPrPb out from CP
    42 73 CF ; Enable Manual Gain and set CH_A gain
    42 74 A3 ; Set CH_A and CH_B Gain - 0FAh
    42 75 E8 ; Set CH_B and CH_C Gain
    42 76 FA ; Set CH_C Gain
    42 7B 06 ; clears the bits CP_DUP_AV and AV_Blank_EN 
    42 85 19 ; Turn off SSPD and force SOY. For Eval Board.
    42 86 1B ; Enable stdi_line_count_mode
    42 8F 77 ; FR_LL to 1820 & Enable 28.63MHz LLC
    42 90 1C ; FR_LL to 1820
    42 BF 06 ; Blue Screen Free Run Colour
    42 C0 40 ; default color
    42 C1 F0 ; default color
    42 C2 80 ; Default color
    42 C5 01 ; CP_CLAMP_AVG_FACTOR[1-0] = 00b
    42 C9 0C ; Enable DDR Mode
    42 F3 07 ; Enable Anti Alias Filters on ADC 0,1,2
    42 0E 80 ; ADI Recommended Setting
    42 52 46 ; ADI Recommended Setting
    42 54 00 ; ADI Recommended Setting
    42 F6 3B ; ADI Recommended Setting
    42 0E 00 ; ADI Recommended Setting
    56 17 02 ; Software Reset 
    56 00 FC ; Power up all DAcs and PLL
    56 01 80 ; SD only mode, Data input on Y-bus
    56 80 10 ; SSAF Luma filter enabled, NTSC mode
    56 82 C9 ; Step control on, pixel data valid, pedestal on, PrPb SSAF on,CVBS/YC out.
    56 84 06 ; RTCO/SFL Enable
    56 88 00 ; 8 bit input enabled
    56 87 20 ; Encoder PAL/NTSC auto-detect enabled
    End
    
    
    
    ##CP 625i##
    :625i/50Hz YPrPb In 8Bit 422 EAV/SAV out Encoder:
    42 05 00 ; Prim_Mode =000b for SD-M
    42 06 0B ; VID_STD=1010b for SD 4x1 525i
    42 1D 47 ; Enable 28MHz Crystal
    42 3A 11 ; Set Latch Clock 01b, Power Down ADC3
    42 3B 81 ; Enable internal Bias
    42 3C 52 ; PLL_QPUMP to 010b
    42 67 13 ; DPP Filters
    42 6B C3 ; Select 422 8 bit YPrPb out from CP
    42 7B 06 ; clears the bits CP_DUP_AV and AV_Blank_EN 
    42 85 19 ; Turn off SSPD and force SOY. For Eval Board.
    42 86 1B ; Enable stdi_line_count_mode
    42 8A B0 ; Manual VCO_RANGE=01
    42 8F 77 ; FR_LL to 1820 & Enable 28.63MHz LLC
    42 90 1C ; FR_LL to 1820
    42 BF 06 ; Blue Screen Free Run Colour
    42 C0 40 ; default color
    42 C1 F0 ; default color
    42 C2 80 ; Default color
    42 C5 01 ; CP_CLAMP_AVG_FACTOR[1-0] = 00b
    42 C9 0C ; Enable DDR Mode
    42 F3 07 ; Enable Anti Alias Filters on ADC 0,1,2
    42 0E 80 ; ADI Recommended Setting
    42 52 46 ; ADI Recommended Setting
    42 54 00 ; ADI Recommended Setting
    42 F6 3B ; ADI Recommended Setting
    42 0E 00 ; ADI Recommended Setting
    56 17 02 ; Software Reset 
    56 00 FC ; Power up all DAcs and PLL
    56 01 80 ; SD only mode, Data input on Y-bus
    56 80 11 ; SSAF Luma filter enabled, NTSC mode
    56 82 C1 ; Step control on, pixel data valid, PrPb SSAF on,CVBS/YC out.
    56 84 06 ; RTCO/SFL Enable
    56 88 00 ; 8 bit input enabled
    56 87 20 ; Encoder PAL/NTSC auto-detect enabled
    End
    
    
    
    ##CP 625i##
    :625i/50Hz RGB In 8Bit 422 EAV/SAV out Encoder:
    42 05 00 ; Prim_Mode =000b for SD-M
    42 06 0B ; VID_STD=1010b for SD 4x1 525i
    42 1D 47 ; Enable 28MHz Crystal
    42 3A 11 ; Set Latch Clock 01b, Power Down ADC3
    42 3B 81 ; Enable internal Bias
    42 3C 52 ; PLL_QPUMP to 010b
    42 52 00 ; Colour Space Conversion from RGB->YCrCb
    42 53 00 ; CSC
    42 54 12 ; CSC
    42 55 90 ; CSC
    42 56 38 ; CSC
    42 57 69 ; CSC
    42 58 48 ; CSC
    42 59 08 ; CSC
    42 5A 00 ; CSC
    42 5B 75 ; CSC
    42 5C 21 ; CSC
    42 5D 00 ; CSC
    42 5E 1A ; CSC
    42 5F B8 ; CSC
    42 60 08 ; CSC
    42 61 00 ; CSC
    42 62 20 ; CSC
    42 63 03 ; CSC
    42 64 D7 ; CSC
    42 65 19 ; CSC
    42 66 48 ; CSC last
    42 67 13 ; DPP Filters
    42 6B C3 ; Select 422 8 bit YPrPb out from CP
    42 73 CF ; Enable Manual Gain and set CH_A gain
    42 74 A3 ; Set CH_A and CH_B Gain - 0FAh
    42 75 E8 ; Set CH_B and CH_C Gain
    42 76 FA ; Set CH_C Gain
    42 7B 06 ; clears the bits CP_DUP_AV and AV_Blank_EN 
    42 85 19 ; Turn off SSPD and force SOY. For Eval Board.
    42 86 1B ; Enable stdi_line_count_mode
    42 8A B0 ; Manual VCO_RANGE=01
    42 8F 77 ; FR_LL to 1820 & Enable 28.63MHz LLC
    42 90 1C ; FR_LL to 1820
    42 BF 06 ; Blue Screen Free Run Colour
    42 C0 40 ; default color
    42 C1 F0 ; default color
    42 C2 80 ; Default color
    42 C5 01 ; CP_CLAMP_AVG_FACTOR[1-0] = 00b
    42 C9 0C ; Enable DDR Mode
    42 F3 07 ; Enable Anti Alias Filters on ADC 0,1,2
    42 0E 80 ; ADI Recommended Setting
    42 52 46 ; ADI Recommended Setting
    42 54 00 ; ADI Recommended Setting
    42 F6 3B ; ADI Recommended Setting
    42 0E 00 ; ADI Recommended Setting
    56 17 02 ; Software Reset 
    56 00 FC ; Power up all DAcs and PLL
    56 01 80 ; SD only mode, Data input on Y-bus
    56 80 11 ; SSAF Luma filter enabled, NTSC mode
    56 82 C1 ; Step control on, pixel data valid, PrPb SSAF on,CVBS/YC out.
    56 84 06 ; RTCO/SFL Enable
    56 88 00 ; 8 bit input enabled
    56 87 20 ; Encoder PAL/NTSC auto-detect enabled
    End
    
    
    
    ##CP 525p##
    :525p/60Hz YPrPb In 8Bit 422 EAV/SAV out Encoder:
    42 05 01 ; PRIM_MODE = 001b COMP
    42 06 06 ; VID_STD for 525P 2x1
    42 C3 46 ; ADC1 to Ain4, ADC0 to Ain6, 
    42 C4 B5 ; ADC2 to Ain5 and enables manual override of mux
    42 1D 47 ; Enable 28.63636MHz crystal
    42 3A 11 ; Set Latch Clock 01b. Power down ADC3.
    42 3B 81 ; Enable Internal Bias 
    42 3C 53 ; PLL QPUMP to 011b
    42 6B 83 ; 422 8bit out 
    42 C9 00 ; SDR mode
    42 73 CF ; Enable Manual Gain and set CH_A gain
    42 74 A3 ; Set CH_A and CH_B Gain - 0FAh
    42 75 E8 ; Set CH_B and CH_C Gain
    42 76 FA ; Set CH_C Gain
    42 7B 1E ; Turn on EAV and SAV Codes.
    42 85 19 ; Turn off SSPD and force SOY
    42 86 0B ; Enable STDI Line Count Mode
    42 8A B0 ; Manual VCO Range=01 
    42 BF 06 ; Blue Screen Free Run Colour
    42 C0 40 ; default color
    42 C1 F0 ; default color
    42 C2 80 ; Default color
    42 C5 01 ; 
    42 C9 08 ; Enable 8-bit mode using psuedo DDR
    42 0E 80 ; ADI recommended sequence
    42 52 46 ; ADI recommended sequence
    42 54 00 ; ADI recommended sequence
    42 57 01 ; ADI recommended sequence
    42 F6 3B ; ADI Recommended Setting
    42 0E 00 ; ADI recommended sequence
    42 67 33 ; DPP Filters
    56 17 02 ; Software Reset
    56 00 FC ; Power up all DAcs and PLL
    56 01 70 ; SELECT INPUT MODE
    56 02 20 ; YPrPb out, SYNC ON
    56 30 04 ; 525p@60 Frame rate, EAV/SAV
    56 31 01 ; ED-HD DATA VALID
    56 32 00 ; ED-HD MODE REG 3
    56 33 68 ; ED-HD MODE REG 4
    56 34 48 ; ED-HD MODE REG 5
    End
    
    
    
    ##CP 525p##
    :525p/60Hz RGB In 8Bit 422 EAV/SAV out Encoder:
    42 7B 1F ; Turn on EAV and SAV Codes. Set BLANK_RGB_SEL. 
    42 05 01 ; PRIM_MODE = 001b COMP
    42 06 06 ; VID_STD for 525P 2x1
    42 C3 46 ; ADC1 to Ain4, ADC0 to Ain6, 
    42 C4 B5 ; ADC2 to Ain5 and enables manual override of mux
    42 1D 47 ; Enable 28.63636MHz crystal
    42 3A 11 ; Set Latch Clock 01b. Power down ADC3.
    42 3B 81 ; Enable Internal Bias 
    42 3C 53 ; PLL QPUMP to 011b
    42 52 00 ; Colour Space Conversion from RGB->YCrCb
    42 53 00 ; CSC
    42 54 12 ; CSC
    42 55 90 ; CSC
    42 56 38 ; CSC
    42 57 69 ; CSC
    42 58 48 ; CSC
    42 59 08 ; CSC
    42 5A 00 ; CSC
    42 5B 75 ; CSC
    42 5C 21 ; CSC
    42 5D 00 ; CSC
    42 5E 1A ; CSC
    42 5F B8 ; CSC
    42 60 08 ; CSC
    42 61 00 ; CSC
    42 62 20 ; CSC
    42 63 03 ; CSC
    42 64 D7 ; CSC
    42 65 19 ; CSC
    42 66 48 ; CSC last
    42 67 33 ; DPP Filters
    42 6B 83 ; 422 8bit out 
    42 C9 00 ; SDR mode
    42 73 CF ; Enable Manual Gain and set CH_A gain
    42 74 A3 ; Set CH_A and CH_B Gain - 0FAh
    42 75 E8 ; Set CH_B and CH_C Gain
    42 76 FA ; Set CH_C Gain
    42 7B 1F ; Turn on EAV and SAV Codes. Set BLANK_RGB_SEL. 
    42 85 19 ; Turn off SSPD and force SOY
    42 86 0B ; Enable STDI Line Count Mode
    42 8A B0 ; Manual VCO Range=01 
    42 BF 06 ; Blue Screen Free Run Colour
    42 C0 40 ; default color
    42 C1 F0 ; default color
    42 C2 80 ; Default color
    42 C5 01 ; 
    42 C9 08 ; Enable 8-bit mode using psuedo DDR
    42 0E 80 ; ADI recommended sequence
    42 52 46 ; ADI recommended sequence
    42 54 00 ; ADI recommended sequence
    42 57 01 ; ADI recommended sequence
    42 F6 3B ; ADI Recommended Setting
    42 0E 00 ; ADI recommended sequence
    56 17 02 ; Software Reset
    56 00 FC ; Power up all DAcs and PLL
    56 01 70 ; SELECT INPUT MODE
    56 02 20 ; YPrPb out, SYNC ON
    56 30 04 ; 525p@60 Frame rate, EAV/SAV
    56 31 01 ; ED-HD DATA VALID
    56 32 00 ; ED-HD MODE REG 3
    56 33 68 ; ED-HD MODE REG 4
    56 34 48 ; ED-HD MODE REG 5
    End
    
    

    in this script doccument ..

    ##CP 625i##
    :625i/50Hz RGB In 8Bit 422 EAV/SAV out Encoder:...this is for 8bit ddr mode..

    To get 12bit ddr mode im going to change 6b register vlaue to 84.Is this is right?

    In this project im configuring the adv7181c register from fpga.

    For advc7181c..h_sync,v_sync,fb,sog are connected to fpga,as these are all the input to adv7181c.

    what should be the value driven for these signal?also what is the register configure for these.