How to find timing definition about Hsync of ADV7343 when using SD mode?

Hi

I want to use ADV7343 in my design.

The mode is SD Only, 8-Bit, 4:2:2 YCrCb Pixel Input Mode to S[7:0],PAL or NTSC mode with R/G/B,CVBS/Y/C output.

By the timing Figure 106 or 107 in datasheet, I could not find the detail timing  description with  S_HSYNC  and S_VSYNC .

Like the relationship between them and pixel data, and how long they need to stay low or high within one horizon time(864 or 858).

By the way. I want to confirm the SD Only, 8-Bit, 4:2:2 YCrCb Pixel Input Mode need to use 54Mhz clock rate, is it right?

Any body know that?

Very king of your answer.

Robin



Thanks.
[edited by: Robin-010 at 1:29 AM (GMT 0) on 14 Feb 2020]