AD9880
Not Recommended for New Designs
The AD9880 offers designers the flexibility of an analog interface and High-Definition Multimedia Interface (HDMI™) receiver integrated on a single chip...
Datasheet
AD9880 on Analog.com
Hi James,
i have pretty much exactly the same issues that you are seeing with the errant syncs when running through the 9880, although i dont see spotty video in this case. my scope captures do not show any reason why the errant syncs occur, except that when i get an errant vysnc and hsync, the errant hsync is always trailing the errant vsync by approx 4ns, or you can see it as each vsync and hsync are lined up with the control bit timing within the CH0 stream during inactive DE. So looking at the CH0 through active dif probes and the snyc outputs doesnt show anything that would allude to why the errant syncs occur, but i'm not too sure if there's a delay between the control bits on CH0 to when the output of the syncs occur.
i have this issue in through my AD FAE and hope to get answers soon. I've attach some scope shots that might be helpful:
datach0errantvsync.bmp is an errant vsync while looking at CH0 stream
errantvsynctop3.bmp, top trace is vsync and bottom trace is hsync and the errant hsync occurs approximately 14 ns after a valid low to high transition, notice the delay of ~4ns from the errant vsync to hsync.
Rolland
Hi Rolland,
Can you capture a full VSync pulse with both leading and trailing edges and the glitch. I'd like to see where the glitch occurs within the VSYNC pulse.
Thanks
Guenter,
The errant sync pulses occur throughout the frame at random periods, however i'm attaching a scope shot that shows both the hsync and vsync glitches while DE should be active, not shown but the hsync and vsync are negative polarity and the glitches occur during the high side of both syncs.
Rolland
Hi Rolland,
A couple of things to try in order:
1) Invert the clock signal and see if this helps, check Register 0x24 bit 0. Of course the clock sink would have to handle the inverted clock correctly.
2) Increase the 1.8V supply to 1.85-1.9V (pins 30, 32 and 48 (if possible)
3) Lower the 3.3V supply to 3.0V (pins 10, 90, 100) (if possible)
Let me know how this works.
Guenter,
I'm figuring out a way to change the voltage on the 1.8 and 3.3V. Can you tell me the reasoning behgind that suggestion and would i have to chnage both or one at time?
thanks,
Rolland
Hi Rolland,
Raising the 1.8V on this part raises the threshold voltage for the incomming TMDS signalling. Lowering the 3.3V will also increase the threshold but not as much as raising the 1.8V.
I'd suggest changing the 1.8V first. Usually it's the easier one to change compared to the 3.3V. Only if that didn't help then change the 3.3V.
Hi James,
We have exactly the same problem with the AD9880.
Could you solve this problem yet!
Thanks, Malikcis
Malickis,
We were able to set the TMDS registers in the AD9880, these are not documented in the datasheets, however we had found the following information from AD to be very helpful
(Note that we found setting Regs 0x53 and 0x59 to 0 instead of what AD recommend, however that is in our setup, your's may be different).
AD9880 TMDS PLL Settings 1-19-06
The recommendations for the AD9880* TMDS PLL settings (register 0x4D - 0x50) are
being updated. These settings will be incorporated into the next revision of the AD9880
data sheet. These settings are a result of more data being compiled through our
Compliance Testing Lab. These settings are outlined in Table 1 below.
Table 1: AD9880 TMDS PLL Settings
Register Old Setting New Setting Description
0x4D 0x36 0x3B Bits[6:4] set the C1 loop filter values (high freq).
Bits [3:0] set the Ch. Pump Current value (high freq)
0x4E 0x36 0x6D Bits [6:4] set the C1 loop filter values (low freq).
Bits [3:0] set the Ch. Pump Current value (low freq)
0x4F 0x33 0x54 Bits [7:5] set the C2 loop filter values.
Bits [4:0] set the R1 loop filter values
0x50 0x20 0x90 This sets the VCO gear manually.
0x53 0x3F 0x3F Phase Recovery Loop control
0x59 0x20 0x20 Controls TMDS clock termination connect
* These settings also apply to the AD9380, AD9381, AD9396, AD9397, and AD9398.
* These settings also apply to the AD9380, AD9381, AD9396, AD9397, and AD9398.
* These settings also apply to the AD9380, AD9381, AD9396, AD9397, and AD9398.
Hi Rolland,
This feedback solved all of our 1080p60 related AD9880 problems.
Thank you very much for sharing this information.
Malikcis,