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DPHY Clock for i.MX8MQ with ADV7282A-M


We are trying to integrate ADV7282A-M with i.MX8MQ using the MIPI CSI2 interface and Linux Kernel.

We are using the open source ADV7282A-M driver: drivers/media/i2c/adv7180.c from Kernel Version 4.14.98 (from NXP BSP: imx-yocto-L4.14.98_2.2.0)

While testing, we are not receiving any frames, however the gstreamer command is not throwing any errors.

It seems that V4L2 QBUF IOCTLS are called, however DQBUF IOCTLS is not called since we are not receiving any frames.

We have few questions in this regard.


Following is my DTS config:

        adv7282_mipi2: adv7282_mipi2@21 {

                compatible = "adi,adv7282-m";

                reg = <0x21>;

                status = "okay";

                pinctrl-names = "default";

                pinctrl-0 = <&pinctrl_csi2_pwn>, <&pinctrl_csi_rst>;

                clocks = <&clk IMX8MQ_CLK_CLKO2>;

                clock-names = "csi_mclk";

                assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>;

                assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>;

                assigned-clock-rates = <20000000>;

                csi_id = <1>;

                pwn-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;

                mclk = <24000000>;

                mclk_source = <0>;

                cvbs = <1>;

                port {

                        adv7282_mipi2_ep: endpoint {

                                remote-endpoint = <&mipi2_sensor_ep>;





I am not certain what should be the MIPI DPHY clock. Currently, I have programmed it to 24MHz.

However, I am observing almost all possible errors on the MIPI controller of i.MX8MQ


root@imx8mqevk:~# /unit_tests/memtool -32 0x30b6010C 1


Reading 0x1 count starting at address 0x30B6010C

0x30B6010C:  0000003E


[0] – crc error
[1] – one bit ecc error
[2] – two bit ecc error
[3] – ULPS status change
[4] – DPHY ErrSotHS has occurred
[5] – DPHY ErrSotSync_HS has occurred
[6] – DPHY ErrEsc has occurred
[7] – DPHY ErrSyncEsc has occurred
[8] – DPHY ErrControl has occurred



Will you have any guidelines on how to debug this. What status registers should I check on the ADV7282A-M side. I am only doing color bar at the moment.



Also, do you have any Test Application (similar to mxc_v4l2_tvin.c) to use to verify the adv7180 Linux Driver. Currently, I am using gstreamer as follows:

gst-launch-1.0 -v --gst-debug-level=2 v4l2src device=/dev/video1 norm=PAL ! 'video/x-raw, format=(string)UYVY,width=720,height=480,framerate=(fraction)30/1,interlace-mode=(string)interlaced' ! videoconvert ! autovideosink

However, many of the driver V4L2 IOCTLS are not being called, for example adv7180_s_std IOCTL callback is not called.


I also noticed an application note:  AN-1337, which mentions the following:

Some MIPI CSI-2 receivers wait for an LP to HS mode
transition on the MIPI CSI-2 clock lane before starting video
capture. However, the LP to HS mode transition on the MIPI CSI-2
clock lane occurs only once on the ADV7280-M, ADV7281-M,
ADV7281-MA, and ADV7282-M immediately after they are
initially programmed.

Is this toggle required for i.MX8MQ MIPI CSI2 Controller. Has anyone faced this issue with imx series processors.

  • Hi,

    Clock signals will only be appeared correctly when it is properly terminated.

    As part of the MIPI specification the MIPI receiver need to terminate the signals correctly.

    If the micro processor/ FPGA does not control the termination correctly then the MIPI signals from the ADV7280-M cannot be decoded.  

    Make sure with XTAL clock - 28.63636 MHz.

    And also if backened processor is not configured correctly and it will pulling the clock lane low - Refer figure 2 of AN-1337.

    For our evaluation of the ADV7280-M we used the MIPI reference termination board available from here:

    By reading AD_Result (0x10,0x12,0x13) status bit register,you can ensure whether input is locked .

    Is this toggle required for i.MX8MQ MIPI CSI2 Controller

     Generally,the backend processor is waiting for a low power (LP) to high speed (HS) transition on the MIPI clock lanes on the ADV7280-M. By default the ADV7280-M will only perform a LP -> HS transition once after it has been configured. It will then remain in HS mode.In LP mode, the data lines have a logic high voltage of approximately 1.2 V and a logic low voltage of approximately 0 V. In HS mode, the data lines have a logic high voltage of approximately 0.3 V and a logic low voltage of approximately 0.1 V. If any logic level other than 1.2 V, 0.3 V, 0.1 V, or 0 V appears, the D-PHY layer of the MIPI CSI-2 receiver is not correctly terminating the output from the ADV7280-M, ADV7281-M, ADV7281-MA, or ADV7282-M transmitter device

    And also please refer here

    Note: In interlaced mode the ADV7282-M outputs with a 216 Mbps data rate (MIPI clock frequency 108 MHz).
    In progressive mode (i.e. I2P mode on) the ADV7282-M outputs a 432 Mbps data rate ( MIPI clock frequency 216 MHz).



  • Hi Poornima,

    Thank you so much for the answer. For some reason, the email went into my spam mail, so saw it late.

    The i.MX8M EVK provides mini SAS connector for MIPI CSI. However, for AD7282 EVM we have SMA connectors. Is there a converter board available in your knowledge. We are planning to build a connector board. Just wanted to check if something like this is already available.

  • Hi,

      Sorry i am not aware of this converter board. Could you please check the same with your local FAE/Salesteam.



  • Hi Poornima,

    Thanks for your reply. I got ADV7282A-m to work with i.MX8MQ. The main changes were the hs_settle ( IOMUXC_GPR_GPR34=00003524) and the toggle of CSITX_PWRDN. It may also be required to change the RX DPHY Core clock to 800MHz but not certain of it. With these changes the CRC and ECC errors vanished. I am using Linux kernel version 4.19.35 from NXP.

    However, I am receiving frames at the rate of 16fps (PAL). I tried programming the ADV by using  the customer scripts. But that did not help either.

    Will you have any comments regarding this. Any registers on the ADV side that I can check.



  • Hi,

    Generally frame rate is fixed depending upon the analog video format that you are using.
      Standard                     Frame Rate
    NTSC Interlaced              30 frames/sec
    NTSC Progressive           60 frames/sec
    PAL Interlaced                 25 frames/sec
    PAL Progressive              50 frames/sec

      It seems like some drop in the frame rate at your side. And also free run mode can help customers to debug issues with their MIPI CSI-2 receiver systems. Please try to use a free-run script and debug your interface issue. Free-run scripts ignore the analog video input and output video test patterns. See AN-1337 for more information. Please make sure with LLC clock(27Mhz) as stable.The default settings in our scripts should give stable output. 

     As per expert comment "The specification highlighted for the receiver is the common-mode interference a High Speed MIPI receiver must be able to reject above 450 MHz, as per the MIPI DPHY version 1.00.00 specification". The specifications highlighted in the ADV7282A-M corresponds to the ADV7282A-M MIPI transmitter output specifications. These conform to the MIPI DPHY version 1.00.00 specification.
     To guarantee optimal operation, the MIPI CSI-2 receiver should also conform to the MIPI D-PHY Version 1.00.00 specification.



  • Hi

    I have the same Problem as described by you with an iMX8MM. Initializing the ADV7282M works fine. But playback in e.g. GST never starts.

    Could you explain how you modified hs_settle and changed the RX DPHY Core clock to 800Mhz?


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