DPHY Clock for i.MX8MQ with ADV7282A-M

Hi,

Clock signals will only be appeared correctly when it is properly terminated.

As part of the MIPI specification the MIPI receiver need to terminate the signals correctly.

If the micro processor/ FPGA does not control the termination correctly then the MIPI signals from the ADV7280-M cannot be decoded.  

Make sure with XTAL clock - 28.63636 MHz.

And also if backened processor is not configured correctly and it will pulling the clock lane low - Refer figure 2 of AN-1337.

For our evaluation of the ADV7280-M we used the MIPI reference termination board available from here:
    https://www.iol.unh.edu/solutions/test-tools/mipi

By reading AD_Result (0x10,0x12,0x13) status bit register,you can ensure whether input is locked .

Is this toggle required for i.MX8MQ MIPI CSI2 Controller

 Generally,the backend processor is waiting for a low power (LP) to high speed (HS) transition on the MIPI clock lanes on the ADV7280-M. By default the ADV7280-M will only perform a LP -> HS transition once after it has been configured. It will then remain in HS mode.In LP mode, the data lines have a logic high voltage of approximately 1.2 V and a logic low voltage of approximately 0 V. In HS mode, the data lines have a logic high voltage of approximately 0.3 V and a logic low voltage of approximately 0.1 V. If any logic level other than 1.2 V, 0.3 V, 0.1 V, or 0 V appears, the D-PHY layer of the MIPI CSI-2 receiver is not correctly terminating the output from the ADV7280-M, ADV7281-M, ADV7281-MA, or ADV7282-M transmitter device

And also please refer here https://ez.analog.com/video/f/q-a/8042/adv7280-m-video-capture-issue-with-i-mx6q/12756#12756

Note: In interlaced mode the ADV7282-M outputs with a 216 Mbps data rate (MIPI clock frequency 108 MHz).
In progressive mode (i.e. I2P mode on) the ADV7282-M outputs a 432 Mbps data rate ( MIPI clock frequency 216 MHz).

Thanks,

Poornima

Hi Poornima,

Thank you so much for the answer. For some reason, the email went into my spam mail, so saw it late.

The i.MX8M EVK provides mini SAS connector for MIPI CSI. However, for AD7282 EVM we have SMA connectors. Is there a converter board available in your knowledge. We are planning to build a connector board. Just wanted to check if something like this is already available.

Hi,

  Sorry i am not aware of this converter board. Could you please check the same with your local FAE/Salesteam.

Thanks,

Poornima

Hi Poornima,

Thanks for your reply. I got ADV7282A-m to work with i.MX8MQ. The main changes were the hs_settle ( IOMUXC_GPR_GPR34=00003524) and the toggle of CSITX_PWRDN. It may also be required to change the RX DPHY Core clock to 800MHz but not certain of it. With these changes the CRC and ECC errors vanished. I am using Linux kernel version 4.19.35 from NXP.

However, I am receiving frames at the rate of 16fps (PAL). I tried programming the ADV by using  the customer scripts. But that did not help either.

Will you have any comments regarding this. Any registers on the ADV side that I can check.

Regards,

Subhasish

Hi,

Generally frame rate is fixed depending upon the analog video format that you are using.
  Standard                     Frame Rate
NTSC Interlaced              30 frames/sec
NTSC Progressive           60 frames/sec
PAL Interlaced                 25 frames/sec
PAL Progressive              50 frames/sec

  It seems like some drop in the frame rate at your side. And also free run mode can help customers to debug issues with their MIPI CSI-2 receiver systems. Please try to use a free-run script and debug your interface issue. Free-run scripts ignore the analog video input and output video test patterns. See AN-1337 for more information. Please make sure with LLC clock(27Mhz) as stable.The default settings in our scripts should give stable output. 

 As per expert comment "The specification highlighted for the receiver is the common-mode interference a High Speed MIPI receiver must be able to reject above 450 MHz, as per the MIPI DPHY version 1.00.00 specification". The specifications highlighted in the ADV7282A-M corresponds to the ADV7282A-M MIPI transmitter output specifications. These conform to the MIPI DPHY version 1.00.00 specification.
 To guarantee optimal operation, the MIPI CSI-2 receiver should also conform to the MIPI D-PHY Version 1.00.00 specification.

Thanks,

Poornima

Hi

I have the same Problem as described by you with an iMX8MM. Initializing the ADV7282M works fine. But playback in e.g. GST never starts.

Could you explain how you modified hs_settle and changed the RX DPHY Core clock to 800Mhz?

Thanks