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CVDD's bypass capacitor of ADV7611.

Hi,

I have some questions about your recommendation of CVDD's bypass capacitor of ADV7611.
Please refer attached file "Questions CVDD bypass capacitor of ADV7611.xlsx".

Thank you!
Best regards.
Tamu

XLSX

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  • FormerMember
    0 FormerMember
on Jan 21, 2020 9:50 AM

Hi Tamu,

First of all every engineer has a slightly different way to couple power rails around chips, that's why you see 2 different schematics implementations.

Instead of pointing to a specific schematic I'll explain a little bit of how I go about doing it which is different from both of these.

The goal of decoupling is to short out noise of high frequency current loops as close to the source as possible.  The current loop would be power pin -> internal ic -> ground pin -> pcb trace -> back to power pin.  The pcb trace might included via.

In general I like to use a chain of caps, 10uf, 1uf & 100nF(10nF) for proper decoupling.  Place a 100nF or 10nF (0402) as close as possible to each single or pair of power pins.  Next closest would be the 1uF (0402/0603).  Depending on power plane design a single 1uF might service a couple of 100nF caps.  The current loop for the 100nF should be smaller than the current loop for the 1uF.

A bulk 10uF cap will provide bulk energy storage for the power plane any normally will only need one cap which is placed outside the 100nF and 1uF cap areas.

On top of this I like to include a power line filter such as a Muratta NFM18PC105R0J3 between the chip and the power source.  This filter will block EMI noise generated on other power rails from coupling into in the rails of interest.

Below is the decoupling used for the ADV7612 eval. board.

There is a great deal of documentation on the web that describes this in more detail, especially optimal layout plans.  Just search for "pcb decoupling layout"

This same layout approach can be applied to all the power rails.

  • Hi GuenterL,

    Thank you for your reply.

    At this time, my customer is going to use ADV7611 and he begins designing the schematic and the layout of his board.
    He asks us the questions.
    My understanding deepened thanks to you, but I don't understand the following two questions yet.

    -------------------------------------------------
    >Question 1:
    >  There is "C6"(1uF) as a bypass capacitor of CVDD on the schematic "adv7611ebz_b_rec.pdf" included in "6013.adv7611_rec_sch_pcb_bom.zip".
    >  How (Where) should the C6(1uF) be physically located?
    >  The CVDD pins are 2pin and 14pin. Which pin should it be brought close to?
    >  We referred the layout guideline "ADV7611_layout_rev0.pdf", but we don't know it.

      There are two CVDD pins of ADV7611, and there are two 0.1uF caps and two 100nF caps on the trace of "adv7611ebz_b_rec.pdf".
      So we can understand that the 0.1uF caps and 100nF caps should be located as close to the each CVDD pins as possible.
      But there is only one 1uF cap(C6), so we don't know How (Where) the C6(1uF) should be physically located.
      I tried to watch the layout file "adv7611ebz_b.pcb", but it was too old to open it.
      Could you indicate the proper location of "C6"(1uF) by a drawing?

    -------------------------------------------------
    >Question 4:
    >  There are some differences between the schem of "adv7611ebz_b_rec.pdf" and "ADV7611_EvalNote_RevA.pdf".
    >  Which schematic do you recommend?

      My customer is going to draw his schematic by making reference to your schematic.
      Which schematic should he refer?
      If both are also fine, I think I will recommend "adv7611ebz_b_rec.pdf" to the customer.

    -------------------------------------------------

    Thank you!
    Best regards.
    Tamu

  • FormerMember
    +1 FormerMember on Jan 22, 2020 9:52 AM in reply to Tamu

    1) I prefer the 'Best Option' below.  The Next option saves a part.  If you remove the EMI filter then these options degenerate into the mentioned schematics.  

    For best results we parallel 2 caps of different values so the cap Q's overlay providing better combined response.

    2) You can use adv7611ebz_b_rec.pdf as a reference.  

    Again look at some of the web search for how to layout these caps.

    I'll be glad to review the schematic and layout when they are ready.

  • Reply
    • FormerMember
      +1 FormerMember
    on Jan 22, 2020 9:52 AM in reply to Tamu

    1) I prefer the 'Best Option' below.  The Next option saves a part.  If you remove the EMI filter then these options degenerate into the mentioned schematics.  

    For best results we parallel 2 caps of different values so the cap Q's overlay providing better combined response.

    2) You can use adv7611ebz_b_rec.pdf as a reference.  

    Again look at some of the web search for how to layout these caps.

    I'll be glad to review the schematic and layout when they are ready.

    Children