CVDD's bypass capacitor of ADV7611.

Hi,

I have some questions about your recommendation of CVDD's bypass capacitor of ADV7611.
Please refer attached file "Questions CVDD bypass capacitor of ADV7611.xlsx".

Thank you!
Best regards.
Tamu

XLSX

Parents
  • 0
    •  Analog Employees 
    on Jan 21, 2020 2:50 PM

    Hi Tamu,

    First of all every engineer has a slightly different way to couple power rails around chips, that's why you see 2 different schematics implementations.

    Instead of pointing to a specific schematic I'll explain a little bit of how I go about doing it which is different from both of these.

    The goal of decoupling is to short out noise of high frequency current loops as close to the source as possible.  The current loop would be power pin -> internal ic -> ground pin -> pcb trace -> back to power pin.  The pcb trace might included via.

    In general I like to use a chain of caps, 10uf, 1uf & 100nF(10nF) for proper decoupling.  Place a 100nF or 10nF (0402) as close as possible to each single or pair of power pins.  Next closest would be the 1uF (0402/0603).  Depending on power plane design a single 1uF might service a couple of 100nF caps.  The current loop for the 100nF should be smaller than the current loop for the 1uF.

    A bulk 10uF cap will provide bulk energy storage for the power plane any normally will only need one cap which is placed outside the 100nF and 1uF cap areas.

    On top of this I like to include a power line filter such as a Muratta NFM18PC105R0J3 between the chip and the power source.  This filter will block EMI noise generated on other power rails from coupling into in the rails of interest.

    Below is the decoupling used for the ADV7612 eval. board.

    There is a great deal of documentation on the web that describes this in more detail, especially optimal layout plans.  Just search for "pcb decoupling layout"

    This same layout approach can be applied to all the power rails.

Reply
  • 0
    •  Analog Employees 
    on Jan 21, 2020 2:50 PM

    Hi Tamu,

    First of all every engineer has a slightly different way to couple power rails around chips, that's why you see 2 different schematics implementations.

    Instead of pointing to a specific schematic I'll explain a little bit of how I go about doing it which is different from both of these.

    The goal of decoupling is to short out noise of high frequency current loops as close to the source as possible.  The current loop would be power pin -> internal ic -> ground pin -> pcb trace -> back to power pin.  The pcb trace might included via.

    In general I like to use a chain of caps, 10uf, 1uf & 100nF(10nF) for proper decoupling.  Place a 100nF or 10nF (0402) as close as possible to each single or pair of power pins.  Next closest would be the 1uF (0402/0603).  Depending on power plane design a single 1uF might service a couple of 100nF caps.  The current loop for the 100nF should be smaller than the current loop for the 1uF.

    A bulk 10uF cap will provide bulk energy storage for the power plane any normally will only need one cap which is placed outside the 100nF and 1uF cap areas.

    On top of this I like to include a power line filter such as a Muratta NFM18PC105R0J3 between the chip and the power source.  This filter will block EMI noise generated on other power rails from coupling into in the rails of interest.

    Below is the decoupling used for the ADV7612 eval. board.

    There is a great deal of documentation on the web that describes this in more detail, especially optimal layout plans.  Just search for "pcb decoupling layout"

    This same layout approach can be applied to all the power rails.

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