I'm sending a color bar image to the ADV7391, the problem is that the output to the TV is not synchronized to the start of frame.
When the PLL is off i.e. Reg 0 bit 1 set to set to 1) the image is constant but not a complete color bar - image number 1, but when the PLL is on the color bar start position is changing for each operation - images 2 and 3 for example.
The digital input to the ADV is similar for each operation.
How do i configure the ADV to show the correct image.
The ADV is configured to work at 720P 60HZ., it should sync on Embedded EAV/SAV codes
Please crosscheck your configuration with below i2c writes as provided in reference script,
54 00 1C ; Power up all DAcs and PLL 54 01 26 ; ED/HD-DDR mode, Y data on DDR rising edge 54 30 2C ; 720p@60 Frame rate, EAV/SAV codes enabled 54 31 01 ; HD4X enabled,Pixel data valid 54 33 6C ; PrPb SSAF , SINC filter enabled, 10 bit input mode enabled 50 11 00 ; FPGA - DCMs out of reset
By configuring register 0x30, We can decide the synchronization format whether it is embedded or external sync.
But by default, the PLL is disabled and also it allows for oversampling of SD,ED,HD video data by enabling.
Basically the problem occur on my custom board not the EVM board but I tried to follow your instruction but I not able to get color bar pattern from the EVM. Please advise if there are more i2c configuration that I need to do. Can the FPGA on the EVM generate color bar to the ADV7391?
On my board I'm doing the same setting you recommended except the part of register 0x33 since I'm working on 8 bits not 10 bits.
54 00 1C ; Power up all DAcs and PLL 54 01 26 ; ED/HD-DDR mode, Y data on DDR rising edge 54 30 2C ; 720p@60 Frame rate, EAV/SAV codes enabled 54 31 01 ; HD4X enabled,Pixel data validReleasing FPGA out from reset.
My questions are:
1. in case of embedded SAV/EAV is there other things the can effect the timing of the ADV output?
2. why when the PLL is enable the ADV output is not constant while when the PLL is off the output is constant?
Let me check with expert on this, why EAV/SAV time codes can't sync on the ADV ..
What is generating the video stream source?
If FPGA then you might not be creating the SAV/EAV bytes correctly or over saturating active video bytes leading to false SAV/EAV signals.
The ADV7391 handles BT.656 fine.
I have two video sources and the ADV is not able to sync on both of them.
The first source is bar generator that is generated by the FPAG.
The second source is a camera which is connected to the FPGA.
In both cases I'm using the SAV and EAV sync word to generate the H and F signals inside the FPGA.
I'm sure the ADV is capable to sync on the SAV and EAV the question is what can cause the ADV to fail ? Is it a missing configuration or any other problem.
From Table 115 which sub-table are you using?
What exact format does the camera output 720p60 16-bit EAV/SAV? If you're not sure link the data sheet and I'll take a look.
I'm using table 124 for the configuration.
The camera output is 720P60 16 bit EAV/SAV.
For 720p 16bit EAV/SAV you should be using Table 116.
Also make sure the exposed pad is connected to ground.
I have 16 bits from the Camera / color Bar generator but I'm using ADV7391 which have only 8 bits of data, therefor I'm using table 124 - 8 bits DDR mode.
The Exposed pad is connected to ground.
You appear to be setting it up correctly. Without a board/system in hand the only thing I can suggest is check the waveforms to make sure they meet the timing requirements. There might be some distortion causing timing issues. I'd also check the system at a slow format than 720p60 if possible.