I use A7 FPGA axi-iic ip and microBlaze ip read/write ADV7604BBCZ-5P question:
1) master read ADV7604 iic address: 0x40, reg:0xc, NACK;
2) master write ADV7604 iic address: 0x40,reg:0xc,val:0x42, ACK
But write iic address 0x4C,iic address 0x44,iic address 0x68, NACK
Please make sure with below things are not happened with other maps, this may cause your part to enter NACK state.
Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, these cause an immediate jump to the idle condition. During a given SCLK high period, the user should issue only one start condition, one stop condition, or a single stop condition followed by a single start condition. If an invalid subaddress is issued by the user, then the part does not issue an acknowledge and returns to the idle condition.
SA Access Problem:
1. AD7604 has multiple SA's in it, according to Hw, SA: 0x40,0X68,0X44,0X4C and other default device addresses should be accessible. But I can only read and write IO MAP SA: 0x40 normally, all other SA reads and writes NACK, and read IO Map subAddress (reg) : 0xF3-0XFE to get the value of 0.
2. After power on, read IO Map SA's subAddress (reg) , most of them only read 0, not the default; but after writing configuration data, I can read the configured value, but there are a few cases where I read 0.
Please make sure below thing, Configure the I2C writes for the desired power-up configuration. This should be done before configuring any Analog Front End (AFE) features or applying any ADI recommended initialization setting. And also try resetting the I2C master after you do the I2C reset command. After a reset, it's recommended to wait 5ms before you attempt an I2C transaction.
Based on the above recommendations, I have the following questions:
I2C reset is the only write that will no ACK back. The reset bit resets the I2c engine before it has a chance to ACK back.The I2C master controller will receive a no acknowledge condition on the ninth clock cycle when chip Reset is implemented. Executing a software reset takes approximately 2 ms. It is recommended to wait 5 ms before any further I2C writes are performed Please refer example read/write sequence for i2c https://ez.analog.com/video/w/documents/14315/i2c-read-and-write-sequence
Note : Need to send STOP bit when the whole process reading is done.To terminate a read/write sequence a stop signal must be sent. Here you can find the more details about i2c bus specification and also timing related details I2C Bus Specification and User Manual