[EVAL-ADV7613FEBZ] LVDS output can not see from "P6" connecter.

Hello.

I have a question for ADV7613 evaluation board (EVAL-ADV7613FEBZ).
Please refer attached file "EVAL-ADV7613FEBZ_Question_191113.pptx".

Thank you!
Best regards.
Tamu

EVAL-ADV7613FEBZ_Question_191113.pptx

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  • +1
    •  Analog Employees 
    on Feb 21, 2020 9:17 AM 11 months ago

    Hi Tamu,

    The functionality of the board as shipped is set. The signals at the output connectors are routed through the FPGA on the board and the connection that you want is not in the FPGA firmware. We are working on an updated version of the board for later in 2020 which will improve on the available muxing. The only opportunity to deliver the functionality you want would be for you to develop RTL for the FPGA.

    Best regards,

    Joe

  • Hi Joe-san and Poornima-san,

    Thank you for your support on EngineerZone. This site is very helpful for me. I frequently browse this site for designing my product that has ADV7613.

    Could you please let me know the development status of the RTL for FPGA on EVAL-ADV7613FEBZ? I would like to know when I can have the RTL because I am now facing exactly the same problem as Tamu-san.

    Best Regards,
    Masa

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