We have designed a board using Zynq ZC702 from Xilinx and ADV7343 for analog video conversion. The data comes from a camera sensor which is interfaced to the Zynq platform via I2C. The incoming 16-bit parallel data is connected to ADV7343 for converting to Y/C and CVBS. This doesn't show any output in the monitor.
To confirm if the hardware is proper, we configured ADV7343 to push internal color bars. This happens properly. After successful verification of this, we connected a TPG source to ADV7343 which was configured for 720x576i in PAL. We do get output color bars on the screen , but there are few issues listed below
These things were observed by noting the path traced by the moving box which was configured from code. We have attached a video of the same and the schematics of our analog section for reference. Our basic assumption was this is due to some sync issues between HSYNC and VSYNC. For this, we played around with different combinations of HSYNC width, polarity, and other parameters, but there is no visible change in performance apart from colors. Colorbars keep changing colors for every different setting. The register setting we have used is also attached.
//Software reset of ADV7343 adv7343_register_write(adv7343,0x17,0x02);adv7343_register_write(adv7343,0x00,0xFC); adv7343_register_write(adv7343,0x01,0x80); adv7343_register_write(adv7343,0x80,0x11); adv7343_register_write(adv7343,0x82,0xCB); adv7343_register_write(adv7343,0x84,0x00); adv7343_register_write(adv7343,0x88,0x0A); adv7343_register_write(adv7343,0x8A,0x0A); adv7343_register_write(adv7343,0x8C,0xCB); adv7343_register_write(adv7343,0x8D,0x8A); adv7343_register_write(adv7343,0x8E,0x09); adv7343_register_write(adv7343,0x8F,0x2A);
Are we doing something wrong?
After making a small change in the hardware design using Vivado (read VDMA channels fsync), we could remove the random noise, but the other issues are still present.
What is the reason for this behavior (Improper color, Shift in origin and split output)? Anyone has faced these errors before?
Your PAL mode register configuration seems different with reference i2c script configuration,Please crosscheck at https://ez.analog.com/video/w/documents/802/adv734x-design-support-files
And also refer page94, there we have configuration script for both PAL and NTSC Mode for CVBS/Y-C output.Please crosscheck your schematic with reference one under ADV734x_Evaluation_Board_Documents.zip
We are giving 16-bit YCbCr data from a sensor and FPGA onto ADV7343. The register settings available in the design files are for 8*bit mode right. Can you help us with the configuration you were referring to?
We tried with Table 79 and Table 80 mentioned in Page 94 of the datasheet, but there is no output.
With the VDMA read channel modification, color bars are coming from TPG but there is a color mismatch between the expected output and output on the screen. We have attached a picture of the same for your reference.
This is what we are getting
This is the output from ADV7343's internal TPG
What is the reason for color mismatch ?
Please crosscheck with below configuration,CVBS out is configured on DAC1.anyhow refer Page51-Table37(Output Configuration)
D6 17 02 ; software resetD6 00 FC ; Power up all DAcs and PLLD6 01 00 ; SD only mode, Data input on S-busD6 80 11 ; SSAF Luma filter enabled, PAL modeD6 82 C3; Step control on, pixel data valid, SSAF on,CVBS/YC out.D6 84 06 ; RTCO/SFL EnableD6 88 08 ; 16 bit input enabledD6 87 20 ; Encoder PAL/NTSC auto-detect enabled
We tried with the settings you had shared, but we are not getting anything out on screen. Is there any specific register which is responsible for proper color reproduction. In the design, our mode of operation was changed from Mode1 slave to Mode 3 slave by setting 0x8A with value 0X0E. This resulted in the shades getting a bit more darker. But there was no proper color reproduction.