adv7181D decode VGA (640 x 480 @60Hz) to 8 bit YUV 422

PCBWe are currently using an ADV7181D to decode VGA (640 x 480 @60Hz) to 8 bit YUV 422.But there is no register

configuration in the script you provided.So I want to ask you something:

1、Does it support doing that  to decode VGA (640 x 480 @60Hz) to 8 bit YUV 422.

2、If yes,could you provide such a script.

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  • +1
    •  Analog Employees 
    on Sep 6, 2019 12:35 PM over 1 year ago

    Hi,

     Yes,there is no configuration script available for VGA to YUV 422 . But you can configure 8bit YUV 422 in register 0x03(OF_SEL) . It allow the user to choose different output format in 8bit,10bit,16bit,20bit in YUV 422.

    Thanks,

    Poornima

  • Thanks for your reply!It works well when we use CVBS signaling,but it didn't work when decoding the VGA signal.We may only use 8bit YUV422 format for hardware reasons.The register 0X03 allow us to choose different output format,but I don't know how to set the other registers because these Settings are professional.So could you provide such a new script and inform the configuration process?
  • I'm sorry, I didn't make myself clear. What I mean is that the VGA signal input has no influence on the output signal of ADV7181D.We know that when CVBS signal is collected, when CVBS signal is not connected, the output of ADV7181D shows a blue screen.But whether the VGA signal is input or not, the phenomenon displayed is the above picture.

    Thanks,

  • 0
    •  Analog Employees 
    on Sep 11, 2019 12:32 PM over 1 year ago in reply to Three

    Hi,

     Please let us know your Tx(DAC). And also try with below configuration.

    42 05 02 ; Prim_Mode =010b for GR
    42 06 08 ; VID_STD=1000b for 640x480 @ 60
    42 C3 31 ; ADC1 to Ain5 (R), ADC0 to Ain2 (G),
    42 C4 F2 ; ADC2 to Ain3 (B), enables manual override of mux, use SOG
    42 1D 47 ; Enable 28MHz Crystal
    42 3A 11 ; set latch clock settings to 001b, Power Down ADC3
    42 3B 81 ; Enable Internal Bias
    42 3C 5C ; PLL_QPUMP to 100b
    42 6A 00 ; DLL Phase Adjust
    42 6B 83 ; Enable DE output, swap Pr& Pb
    42 C9 08 ; Set DDR_EN
    42 73 90 ; Set man_gain
    42 7B 1D ; TURN OFF EAV & SAV CODES Set BLANK_RGB_SEL
    42 85 03 ; Enable DS_OUT
    42 86 0B ; Enable stdi_line_count_mode
    42 0C 36 ;DEF_VAL_AUTO_EN bit set to high when ADV7181D lost lock.
    42 8A 90 ; VCO Range to 00b
    42 F4 3F ; Max Drive Strength
    42 0E 80 ; ADI Recommended Setting
    42 52 46 ; ADI Recommended Setting
    42 54 80 ; ADI Recommended Setting
    42 0E 00 ; ADI Recommended Setting
    42 52 80 ; ADI Recommended Setting
    42 57 08 ; ADI Recommended Setting
    42 5B 00 ; ADI Recommended Setting
    42 5C 01 ; ADI Recommended Setting
    42 62 20 ; ADI Recommended Setting
    42 63 00 ; ADI Recommended Setting
    42 67 03 ; ADI Recommended Setting
    42 68 01 ; ADI Recommended Setting

    Thanks,

    Poornima

  • Hi,

       When we collect CVBS signals, the configuration script provided by you is "AUTODETECT CVBS IN NTSC/PAL/SECAM, 8-Bit 422 encoder".This is the CVBS signal that we connected to the camera, which is displayed, and the effect is quite good.

        Of course, I also compared these two scripts and found the differences in registers 0x6b, 0xc9 and 0x7b, and I found that our MCU could not collect the data output of ADV7181 when configuring the 0x7b register.

        When we do not configure register 0X7B, the effect is the same as the configuration script you provided last time,Our MCU can collect some data, as shown in the figure below, but the VGA signal input has no impact on the signal output of ADV7181D.

  • 0
    •  Analog Employees 
    on Sep 12, 2019 1:04 PM over 1 year ago in reply to Three

    Hi,

     After configuring this "42 0C 36 ;DEF_VAL_AUTO_EN bit set to high when ADV7181D lost lock". You could able to get the freerun output ?

    And also please let us know your Tx(DAC -Encoder)?

    Below thread seems they could get the 16bit 422 from VGA input,the same only we did for 8bit 422 by changing 0x6B register. Please crosscheck

    https://ez.analog.com/video/f/q-a/10184/adv7181d-vga-decoding-to-16-bit-yuv422

    Thanks,

    Poornima

  • Yes, After configuring this "42 0C 36 ,I  get the freerun output(blue screen), and I found that VGA input can affect the display, but of course the display is not correct.

     I'm sorry,I don't understand the DAC-Encoder what you mean,Could you explain?

    I also believed that ADV7181 could realize my idea. As I was not familiar with the configuration of ADV7181,so I'm in trouble.

Reply Children
  • 0
    •  Analog Employees 
    on Sep 18, 2019 6:04 AM over 1 year ago in reply to Three

    Hi,

     Referred thread seems,they managed to get 16 bit YUV422. Please try with scripts as they mentioned for the ADV7181D (:RGB  1024x768 _@ 60Hz 12-Bit DDR 65.000MHz Out through HDMI:) and the scripts for the ADV7401 (:TT 1024x768 @_60Hz, 16 Bit 422 YCrCb SD Space Out from Decoder. Here we don't have evalboard to check.

     ADV7181D is decoder,i.e ADC(Analog input to digital output), So this digital output is feeding into DAC like ADV739x,ADV7341.

    Thanks,

    Poornima

  • I reorganized my thoughts.

    First, when the input signal is VGA, ADV7181D needs to use CP mode.Isn't it?

    Second, we look at register 0x6b and find that 8bit YUV422 DDR can be output in CP mode, but 8bit YUV422 cannot be output.

    DDR refers to Double Data Rate,but  I can't use it.

    So can I assume that I'm indicating output in either 16bit or 20bit YUV422 format?

    Third, if I use 16bit yuv422, I have a question: if I input VGA 1280*720@60 and register 0x06 sets XVGA (1024x768@60) mode, will the image acquisition be incomplete?

    Looking forward to yourreply!

  • 0
    •  Analog Employees 
    on Sep 19, 2019 1:40 PM over 1 year ago in reply to Three

    Hi,

     First, when the input signal is VGA, ADV7181D needs to use CP mode.Isn't it?

      The ADV7181D contains two main processing sections. The first section is the standard definition processor (SDP), which processes all PAL, NTSC, and SECAM signal types. The second section is the component processor (CP), which processes YPrPb and RGB component formats, including RGB graphics.

    DDR mode nothing but the pixel output port can be configured in an 8-/10-/12-bit 4:2:2 YCrCb upto a clock rate of 75Mhz.

    Third, if I use 16bit yuv422, I have a question: if I input VGA 1280*720@60 and register 0x06 sets XVGA (1024x768@60) mode, will the image acquisition be incomplete?

         If you read register 0x06,whether its showing 1280*720@60 or 1024x768@60 ?why you are changing 0x06 register ?

    Thanks,

    Poornima

  • Hi,

       I saw it in data sheet "9.3 CP DDR Output Interface" that :The ADV7181D allows data to be output in a DDR mode up to a clock rate of 75 MHz. In DDR mode, a new data value is presented on the positive and the negative edge of the LLC (line-locked clock) and, hence, double the amount of data is transferred.

       It does not support DDR mode that the MCU we used.So I think what I need is that can output 8-bit YCbCr 4:2:2 in SDR mode out of the CP core.

       https://ez.analog.com/video/f/q-a/5109/adv7181d-vga-decoding-to-8-bit-yuv422 

      It mentioned in this thread :it is not possible to output 8-bit YCbCr 4:2:2 in SDR mode out of the CP core.

  • 0
    •  Analog Employees 
    on Sep 25, 2019 2:43 PM over 1 year ago in reply to Three

    Hi,

    It mentioned in this thread :it is not possible to output 8-bit YCbCr 4:2:2 in SDR mode out of the CP core ?

       Yes,Its not possible without CP Core. Refer here  https://ez.analog.com/video/f/q-a/7091/adv7181-cp-8bit-mode

    Note: SDR 8-/10-bit 4:2:2 YCrCb for 525i and 625i
    SDR 16-/20-bit 4:2:2 YCrCb for all standards

    Thanks,

    Poornima