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AD9380 BCAPS value

Customer would like to limit the DDC I2C clock rate to 100 kHz. Using an HDMI analyzer, he sees the AD9380 provide the BCAPS value of 0x13, indicating FAST - the device supports 400 kHz; 1.1 Features are supported; Fast_Reauthentication is supported.

It is also strange that bit 7 is cleared. From HDCP 1.1:

What is the method used to set BCAPS to clear the FAST bit or the other bits of the BCAPS register? I did not find a register or pin configuration in the datasheet.

BCAPS Bit 7: HDMI_RESERVED Use of this bit is reserved. HDCP Receivers not capable of supporting HDMI must clear this bit to 0.

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